Tuesday, September 14, 2010

Recap from the PAST - the last decade!

Verification has evolved a lot in the past 2 decades and there is more to come as we step in the next decade. This 3 part series lists out the highlights of the past, the present & predictions for the future.

Nineties had a crucial role in justifying verification to get a prominent berth in ASIC design cycles, ASIC schedules and ASIC teams. It was during this decade when verification commenced with full pace. Following are some milestones that helped achieve this. Some of them peaked & stagnated while others blossomed to scale even bigger in the following decade.

1. Standardization of HDLs and ownership of revised versions.
- VERILOG - IEEE 1364-1995 [Latest version 1364-2001, 1364-2005]
- VHDL - IEEE 1076-1987 [Latest version 1076-1993, 1076-2002]
- (OVI) Open Verilog International and VHDL International merged in 2000 to form Accellera.

2. The Simulator war.  Following are the ones that received wide acceptance -
- Verilog XL [Interpreter]
- VCS (Verilog compiled simulator) [Compiler]
- Modelsim

3. Directed verification - With low gate count, HDLs/C based verification was the softest path to tapeout. The test plans and test benches were primitive enough targeting only the features to be verified with no scalability & reusability.

4. Defined verification teams - With increasing design size (gate count) and  complexity there was a need to parallelize the effort of RTL with verification. Other factors like, having second pair of eyes to look into code and verification comprising 70% of asic schedule etc. ignited the look-out for dedicated verification teams to tame the bugs in the design.

5. Automation of verification infrastructure - The increasing complexity and no. of tests were a challenge to manage. Scripting took the front seat to automate the whole process of verification which includes, running tests in batch mode, checking for failures, regressions etc.  Typically every organization had a script called runsim as a initial step to get the flow working.

6. Constrained random verification - With design advancements poised to follow Moore's law directed verification saturated and there was a need for controlled aka constrained random stimuli to uncover unforseen bugs. C++ came up to rescue followed by hardware verification languages like Vera & e.

7. Code coverage - Increasing verification complexity lead to the basic but intricate question - 'are we done'? Covering the RTL code with the given set of stimuli has been one of the important milestone defining closure since then.

8. Gate level simulations - With equivalence checkers still stabilizing, setting up gate level simulations flow was crucial to ensure the synthesized netlist was sane enough to go for a tapeout.

9. Hardware accelarators - The concept of FPGA prototyping was replicated to develop boxes that could synthesize the design and run them 10x or faster to reduce the test case turn around from days to hours.

10. ASIC design as part of the curriculum was introduced at institutes in India offering Micro-electronics/VLSI as a subject in graduation and as a complete stream for post graduation. This helped source engineers to meet the demand for the semiconductor industry.

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