Sunday, October 26, 2014

Verification and Firecrackers

Last week, the festive season in India was at its peak with celebrations everywhere. Yes, it was Diwali - the biggest and the brightest of all festivals.
Diwali aka Deepawali means a 'row of lights' (deep = light and avali = a row). It’s the time when every house, every street, every city, the whole country is illuminated with lights, filled with aroma of incense sticks, delicious food and sounds of fire-crackers all around. People rejoice paying their obeisance to the Gods for showering health, wealth and prosperity. For many, besides the lights & food, it the crackers that is of supreme interest. The variety ranges from the ones that lighten the floors and the sky to the once that generate a lot of sound. On the eve, while everyone was busy in full ecstasy an interesting observation caught my attention initiating the neurons in my brain to connect it to verification resulting into this post.

The Observation

While enjoying, typically the groups get identified based on age or preference for firecrackers. Usually the younger ones are busy with the stuff that sparkles while the elder ones get a kick with the noisy ones. A few are in transition from light to the sound with some basic items. The image below shows a specific type of firecrackers both bundled and dismantled. 

                                                          Source : Google (

The novices were busy with the single ones bursting one at a time. A hundred of such pieces would probably take 50 minutes or so almost linearly progressing. If one of them didn’t burst, they would actually probe and see that it worked or threw it. On the other hand the grownups were occupied with the bundled ones that once fired would go on till all of them gave out the resulting light and sound. More the no. of pieces, the longer it would take but the time was much less then releasing individual pieces. It was hard to identify if a 100 pieces bundle actually resulted in 100 sounds or not but overall the effect was better.

The Connection

Observing the above, I could quickly connect it to the learning we have been through as verification engineers. It was directed tests initially wherein we would develop one test at a time and get it going. The total time to complete all the tests was quite linear and for limited number of tests the milestones were visible. Slowly we incorporated randomness into verification where a bundle of tests could run in a regression hitting different features quickly. The run time is dependent on the no. of times the tests run in random regression. Yes, this also results in redundancy but the gains are more especially if the no. of targets is more. 

The Conclusion

As for the firecrackers, the novices playing with individual ones may move to the bundles next year – a natural progression! This is an important conclusion as it demonstrates the learning steps for verification engineers too. Knowing SV & UVM is good but that doesn’t make one a verification engineer. A verification engineer needs to have a nose for bugs and develop code that can hit them fast and hard. This learning is hidden in working on directed tests initially and transitioning to constrained random thereafter. You would appreciate the power of the latter in a better way!

Try extrapolating it more to different aspects of verification and I am sure you would find the connections all throughout. Drop in a comment on your conclusions!

Disclaimer: The intention of the blog is not to promote bursting crackers. There are different views on the resulting pollution and environment hazards that the reader can view on the web and make an individual choice.

Sunday, October 12, 2014

Moving towards Context Aware Verification (CAV)

The race between predictions vs. achievement of Moore’s law has had multi-fold impact on the semiconductor industry. Reuse has come to the rescue both from the design and verification viewpoint to help teams achieve added functionality on a given die size. This phenomenon lead to the proliferation of IP & VIP market. Standardization of interfaces further enables this move by shifting the product differentiation towards architecture and limited proprietary blocks. To enable continued returns and cater to different application segments, the IP needs to be highly configurable. 

Verifying such flexible IP is a challenge; integrating it for a given application and ensuring that it works, further complicates the problem. Given that verification already claims majority of the design cycle efforts, it is important to optimize on the resources, be it tool licenses, simulation platform or engineer’s bandwidth. A focused attempt is required so as to ensure that every effort converges towards the end application i.e. the context in which the design would be used irrespective of the flexibility that the silicon offers. This refers to the subject Context Aware Verification (CAV)!

Verification space has been experiencing substantial momentum on multiple fronts so as to fill the arsenal of the verification engineer with all sorts of tactics required for the challenges coming our way. While these developments are happening independent of each other, they seem to converge towards enabling CAV. Let’s take a quick look at some of these techniques –

Traditionally, test plan used to answer what is to be verified until constrained random entered the scene where how to verify, what to verify and when are we done needs to be addressed by the verification plan. Today verification planner tools enable us to develop executable verification plan with the flexibility to tag the features based on engineer who owns it or based on milestones or based on priorities and above all based on any other custom definition. This customization is useful to club features with reference to a particular context or configuration in which the IP can operate. With this information, the end user of the IP can channelize his efforts in a particular direction rather than wandering everywhere thereby realizing CAV in the larger scheme of things.

Apart from coverage goals that get defined as part of the vplan, there is a need of a subset of tests that would achieve these goals faster. What this means is that the test definition needs to be -
- Scalable at different levels (IP, sub system & SoC)
- Portable across platforms (constrained random for block level, directed tests for SoC verification & validation) 
- Provide a possibility of tagging the tests w.r.t. a given configuration viz a set of valid paths that the design would traverse in the context of a given application. 
Graph based verification is a potential solution to all of this. There is a need to standardize the efforts and to enable discussions in this direction Accellera has initiated Portable Stimulus Proposed Working Group. Once there is a consensus on the stimuli representation, selection of a subset of tests targeting a given configuration would further boost CAV.

With design size marching north, the simulation platform falls short in achieving verification closure in a given time. A variety of emulation (HW acceleration or prototyping) platforms provide an excellent option to speed up this process based on the design requirements. While the verification teams benefit from the simulation acceleration, these boxes also help in early software development and validation. The shift left approach in the industry is enabling basic bring up of OS and even simulating real time apps on these platforms much before the silicon is back. Ability to run the end software on the RTL brings further focus and is an important step towards achieving CAV.

Once all these technologies reach maturity a combined solution would bring in the required focus in the context of the end application. 

As Chris Anderson said – In the world of infinite choice, context – not content – is king!

Our designs with myriad configurations are no different. It is the context that would bring in convergence faster making those products that follow this flow as king!

Saturday, October 4, 2014

DVCON India 2014 : Event Recap!

It’s been a week and we are still receiving messages and emails on the success of the first edition of DVCON in India. The campaign kicked off a few months back and the team put in relentless efforts for the success of this event. There was an overwhelming response from the ESL and DV community once the call for abstracts got announced. Panelists in both the tracks conducted multiple reviews for every paper and after long discussions the chosen ones were intimated for the presentations. The content of the papers were a clear indication of the quality of work and due diligence that is put in by engineers in this geography. Abstracts were submitted from authors outside India too and many traveled to present it on Sept 25-26 2014.

When I reached early morning the corridors, the halls and the stage were all set to kick start the 2 days filled with learning, sharing and networking. While the registrations (paid) prior to the event indicated expected numbers, scores of spot registrations further added the icing to the cake. Interestingly, the halls were full by 9:30 AM and the program kicked off in time with the lamp lighting ceremony and welcome note from Umesh Sisodia – Chair DVCON India 2014. Dr. Walden C. Rhines – CEO Mentor Graphics mesmerized the crowd with his keynote on 'Accelerating EDA innovation through SoC designmethodology convergence'. We couldn’t have asked for a better start! Next, Dr.Mahesh Mehendale - CTO, MCU at Texas Instruments threw an excellent insight on 'Challenges in the design and verification of ultra-low power “more than Moore” systems'. The mood of the conference was all set with the success of the first session. The conference bifurcated from here into ESL and DV tracks with interesting topics getting discussed as part of invited talks. During teak breaks, lunch hour and evening cocktails, the long galleries were full with chit chat between engineers, exhibitors and poster presenters. After lunch, 4 tutorials started in parallel with industry pundits talking about technologies that are into mass adoption and what to look for next. All sessions were jam packed with audience eager to ask questions during the sessions and continue that inquisitiveness till the day wrapped up with informal meetings during the cocktail.

DAY 2 witnessed the same zeal and enthusiasm. It started off with Ajeetha Kumari – Vice Chair, DVCON India 2014 welcoming the audience followed by Dennis Brophy – Vice Chairman Accellera sharing insights on different working groups within Accellera and inviting engineers to actively participate and contribute. Next was the guru Janick Bergeron – Verification fellow, Synopsys talking about 'Where is the Next Level of Verification Productivity Coming from?' The morning session wrapped up with keynote from Mr. Vishwas Vaidya – AGM, Electronics, Tata Motors discussing 'Automotive Embedded Systems: Opportunities and Challenges'. From there on, it was the papers & posters running into 4 to 5 parallel tracks with engineers sharing the challenges they faced and the solutions they discovered as part of this process. Yes there was an award for the same and the judges were none other than the audience themselves casting their vote by end of all sessions. The crowd continued to stay back anxious to know the results and participate in a series of lucky draws that followed. While a wide variety of topics got covered on DAY 2, the results were all in favor of UVM papers clearly confirming of what Dr. Wally Rhines presented as a starting point that India leads in adoption of System Verilog and UVM across the world (based on a latest survey). 

By the Day 2 evening the corridor, the halls and the stage were silent again, maybe exhausted of experiencing the 2 day long sessions, maybe enjoying the recap of the eagerness shown by  400+ delegates, maybe feeling proud of their contribution to the history for hosting the first DVCON in India.  

Many congratulations for those who were able to experience the event and be part of this historical moment. Live tweets for the event can be searched with #DVConIndia on twitter. The proceedings, photographs and videos of the event will be made available soon on the official website If you missed this year, make sure you make it for the next year event which would be surely bigger & better!!!

Yours truly presented an invited talk “...from Nostalgia to Dreams ...the journey of verification” on DAY 1. Stay tuned for a few blogs from that discussion!