Accellera board approved the UVM 1.0 standard on FEB 18, 2011 after months of hard work and collaborative efforts from the VIP TSC members. Accellera also hosted a day-long UVM tutorial on 28th FEB at DVCon, San Jose, attended by a record breaking audience. The release includes a Class Reference manual, an open-source SystemVerilog base class library implementation, and a User Guide. A copy of the UVM tutorial is also available from Accellera website.
While UVM addresses the basic issues experienced by the verification community (see blog, UVM : Recap before Release) it also opens up interesting opportunities for everyone.
- VIP suppliers don’t need to maintain the VIPs for multiple methodologies. The development, maintenance and support efforts can now be directed in broadening the portfolio instead.
- Standardizing the methodology eliminates redundancies and provides a solid platform for VIP development. We could soon see “VIP store” similar to the “app store”.
- Many EDA vendors maintain a strong VIP portfolio. So far, the VIPs offered were based on the methodology they supported. Even if they had a robust product, the chance of winning a deal with a customer using a simulator from competition was highly unlikely. Now with UVM, everyone gets a fair chance and the best match wins.
- Verification teams will not have to think a lot while switching simulator vendors for business or technical reasons. A verification environment developed in UVM should work on all simulators without a lot of rework. This would improve competition among the EDA vendors thereby benefiting everyone at large.
- Project teams, get a chance to evaluate the third party VIPs on a common platform without dumping any vendor based on extra effort required to simulate the VIP with other simulators. Benchmarking and decision making becomes easy.
- Project teams can also plan to develop the verification environment based on VIP from one vendor and have a few licenses from one more vendor to make sure on the protocol compliance without developing the whole environment from scratch. A second pair of eyes is always considered worthy to roll out quality products.
- With increasing complexity on SOC, having sub-systems as IPs is inevitable. A standardized verification methodology would accelerate the development and integration of such sub-systems into SOC with minimal efforts.
- Finding verification engineers who can be quickly productive has always been difficult. With UVM, project teams should be able to find engineers who can be deployed without a lot of ramp up on alternate methodologies.
Most of the semiconductor companies have already shared that they have teams already working on UVM. For all new project starts, going with UVM is the right choice.
Recently in India, mobile number portability kicked off. Consumers can keep the same cell number while switching service providers. UVM provides a similar platform for verification teams. With environments developed in UVM, switching vendors, playing around with VIPs from multiple vendors and realizing better products would be relatively less painful. UVM definitely is a step forward towards overcoming the verification challenges of tomorrow.
If you are already working on UVM drop in a note with your experiences. If you haven’t thought of UVM so far then ACT NOW!!!
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