Saturday, January 29, 2011

UVM : Recap before Release

With UVM1.0 all set to release, here is a quick recap on the journey so far.
Verification started off with the regular HDLs. As design complexity increased, HVLs were introduced to accomplish this task. The need to maximize returns lead to development of (BCL) base class libraries (using HVLs). This facilitated realization of verification environment across multiple projects in an organization efficiently. To avoid maintainability issues, this task was left with the EDA vendors who morphed these BCLs into methodologies defining everything that needs to be there in a verification environment. Time to market pressure pushed reusability for common modules & protocols in design as well as verification. Soon Verification IPs (VIP) with different HVLs and methodologies came forward. The common HVL & methodologies include Specman-e with eRM, Vera with RVM and System Verilog with OVM/VMM. Different HVLs & methodologies opened up issues related to interoperability i.e. –
-    Developing a verification environment with VIPs in different languages and methodologies.
-    Not all HVLs and methodologies would work with given set of simulation tools.
During all this, System Verilog took a lead to become most commonly used HVL with OVM & VMM as the prime methodologies. In 2008, Accellera, an industry standard organization took the charge to address the above issues and formed a VIP-TSC (Verification IP – Technical subcommittee). By June 2009, the team came up with ‘Recommended Guidelines for Interoperability between VMM and OVM. Next they started off with a proposal defining UVM i.e. Universal verification methodology with the goal to solve the interoperability problem while providing the best of available methodologies.
UVM 1.0 EA

In May 2010, VIP TSC released UVM1.0 EA (Early Adopter) with following salient features –
-     This release was based on (but not 100% backward compatible with) OVM 2.1.1
-     Modified and enhanced objection mechanism
-     Modified and enhanced callback mechanism
-     Added a new report catcher and messaging mechanism  
-     Few deprecated features of OVM removed completely

Along with a standard, this release included – a user guide, a reference manual and an open source reference implementation.
For OVM users to migrate to UVM 1.0 EA, it was pretty straight forward. With help of a script the change of names (ovm_ to uvm_, OVM_ to UVM_, tlm_ to uvm_tlm_, and TLM_ to UVM_TLM_) was quick. If the OVM test bench was using objection and callback mechanism then that required modification to be UVM compatible.
For VMM users, a VMM-UVM interoperability library was made available to enable ease of migration.

UVM1.0 – what to expect?

With UVM1.0 release all set to hit the mainstream in a couple of week’s time, here is what one can expect from that release –
-     Register package. Based primarily on VMM RAL and modified to fit into UVM.
-     Improved Phasing mechanism. Mainly divided into 3 phases [Initialization, Execution and Termination], with each phase further sub-divided into multiple sub phases. This new scheme will provide enhanced test bench control to the user.
-     Resource manager. An updated form of configuration mechanism from previous release to handle different components & objects of test bench with more ease and effectiveness.
-     Command line options made available in form of a data structure to be used in developing and controlling complex test benches.
-     In built support for TLM (Transaction level modeling) based on OSCI (Open SystemC initiative) TLM-2.0 standard.
-     Backward compatibility with UVM1.0 EA.
-     Clean from bugs reported for UVM1.0 EA.

What next?

Beyond successful UVM1.0 release we can expect the VIP TSC team to start looking into -
-     Feature improvement from UVM1.0 based on the feedback
-     Additional System Verilog based methodology features
-     Support for different HVLs or a scheme to integrate various VIPs developed using different HVLs with UVM environment
-     New features to support Low power verification
-     Support for hardware accelerators and virtual prototyping

Hats off to the VIP TSC team for putting efforts in defining a one stop solution for the verification worries.


  1. Response from UVM professionals group

    Adam Sherer • Good summary!

    Satbinder Singh Ram • Nice overall view. Thanks

  2. UVM professionals linkedin group -

    Dennis Brophy • Gaurav, your post is a very succint status of the UVM 1.0 contents. The Accellera VIP-TSC will hold a one-day workshop on UVM 1.0 at DVCon 2011 in San Jose, CA USA. While this may be a hard place for many to reach, several of us are working to see if we can at least post at PDF of the workshop slides to allow the global community of UVM users to have the same access to UVM details as those attending the daylong workshop. Details on the workshop can be found at