In the last 3+ decades, verification has come a long way! Right
from quick testing by designers to dedicated verification teams moving from directed testing to constrained random and adding elements of formal apps at times, it has been an eventful journey! Standardization of UVM enabled a common framework with which the fraternity marched forward in sync with each other. Horizontal reuse viz. at the IP level experienced maximum benefits
of UVM while vertical resume viz. from
IP to SoC level observed limited returns. Apart from the methodology, verification
has also proliferated beyond simulation or emulation into virtual prototyping, FPGA
validation, post silicon functional validation & HW SW co-verification. Today,
the reuse aspects are not limited from IP to SoC or across projects but between platforms too. It is extremely important to realize reuse of efforts at any level across different
vehicles enabling first silicon success. The challenge however is that each of
these vehicles involve multiple stakeholders like architects (Chip , SW,
system), SystemC modelling engineers, RTL designers, verification engineers, prototyping
experts, post silicon debuggers and SW developers, each defining & driving
the stages of SoC design cycle. Different goals focusing on a specific stage, different
approaches in solving these problems and different means of representing solutions
has made the task of reuse across the platforms – a convoluted puzzle!!!
To solve this problem, Accellera initiated a task force
called Portable Stimulus Working Group (PSWG) that reviewed the concern &
potential solutions. After long & regular sessions of intense activity in
last couple of years, the group has come up with a proposal in form of a
standard. Beta release of the preliminary
version of the Portable Test and Stimulus Standard is now opened for public review.
The basis of the solution relies upon taking the stimulus
definition across platforms to an abstraction layer where the focus is on what
is needed instead of how it shall be implemented? The idea is to understand
& represent the action/outcome i.e. the behavior of the DUT when the test runs.
While representing these actions, the focus would be on what would be the
inputs and outputs, what resources are required in the DUT, and their relationship with each other? The how part i.e. the implementation will
be left to a hidden layer (read EDA tool) to generate the required stimulus for
the target platform based on the scenario definition. The actions referred above are all declarative and not procedural or executable by themselves. A set
of these static actions can be used to construct a scenario, analyzed for
coverage to determine the paths to be traversed & dumped into a test format
using the hidden layer.
To represent these actions, the PSWG has proposed 2 formats -
Domain Specific Language (DSL) that is close to System Verilog and a restricted C++
library. Both these formats have equivalent semantics that are completely
interchangeable such that for each line in the DSL there is an exactly equivalent
C++ library entry. If one defines the actions of an IP in DSL and another
IP in C++ library, both can be read together to generate a SoC level scenario for the
target platform.
While the road of moving from developing each testcase to a testbench
that generates tests has been long, it’s time to take another step in the direction of standardizing the stimuli!
This would feed the testbenches for IP/SoC verification & be reused by other
workhorses of verification & validation in the SoC design cycle. Remember, reuse is one of the keys to keep up with Moore's law!!!
The public review period for this proposal is open until
Friday, March 30, 2018. Download & review NOW!!!
