Back to the basics : Power Aware Verification - 1

The famous quote from the movie 'Spiderman' – “With great power comes great responsibility” gets convoluted when applied to the semiconductor industry where “With LOW power comes great responsibility”. The design cycle that once focused on miniaturization, shifted gears to achieve higher performance in the PC era and now in the world of connected devices it is POWER that commands most attention. Energy consumption today drives the operational expense for servers and data centers so much so that companies like Facebook are setting up data centers close to Arctic Circle where the cold weather reduces cooling expense. On the other hand, for consumer devices ‘meantime between charging’ is considered as one of the key factors defining user experience. This means that environment friendly green products resulting from attention to low power in the design cycle can bring down the overall cooling/packaging cost of a system, reduce probability of system failure and conserve energy.

DESIGN FOR LOW POWER

The existing hardware description languages like Verilog & VHDL fall short of semantics to describe the low power intent of a design. These languages were primarily defined to represent the functional intent of a circuit. Early adopters to the low power design methodology had to manually insert cells during the development phase to achieve the desired results. This process was error prone with limited automation and almost no EDA support. Archpro, an EDA startup (acquired by Synopsys in 2007) provided one of the early solutions to this space. Unified Power Format (UPF – IEEE 1801) and Common Power Format (CPF from Si2) are the two TCL based design representation approaches available today to define a low power design intent. All EDA vendors support either or both formats to aid development of power aware silicon.

VERIFYING LOW POWER DESIGN

Traditional simulators are tuned to HDLs i.e. logic 1/0 and do not have a notion of voltage or power turning on/off. For the first generation of low power designs, where cells were introduced manually, the verification used to be mostly script based by forcing X (unknown) on the internal nodes of the design and verifying the outcome. Later, when power formats were adopted for design representation, the verification of this intent demanded additional support from the simulators such as –

- Emulating the cells like isolation, state retention etc. during the RTL simulations to verify the power sequencing features of the design. These cells are otherwise inserted into the netlist by the synthesis tool taking the power format representation as the base

- Simulating power ON/OFF scenarios such that the block that is turned off has all outputs going X (unknown)

- Simulating the voltage ramp up cycle which means once the power is turned ON, it takes some time for the voltage to ramp up to the desired level and during this period the functionality is not guaranteed

- Simulating multi voltage scenarios in the design and in absence of level shifter cells the relevant signals are corrupted

- Simulating all of the above together resulting into a real use case scenario

Tools from Archpro (MVRC & MVSIM) worked with industry standard simulators through PLI to simulate power aware designs. Today all industry standard simulators have the feature to verify such design with limited or complete support to the UPF & CPF feature list. Formal/Static tools are available to perform quick structural checks to the design targeting correct placement of cells, correct choice of cells, correct connections to the cells and ensuring power integrity of the design based on the power format definition at RTL and netlist level. Dynamic simulations further ensure that the power intent is implemented as per architecture by simulating the power states of the design as functional scenarios. 

CONCLUSION

In the last decade, the industry has collaborated at different levels to realize power aware design for different applications. Low power was adopted for the products targeting the consumer and handheld markets initially but today it is pervasive across all segments that the semiconductor industry serves. The key is to define the low power intent early and incorporate tools to validate that the intent is maintained all throughout. As a result, low power lead to greater responsibility for all stakeholders to the design cycle in general and for the verification engineers in particular!

DVCON 2014 issue of Verification Horizons has an article “Taming power aware bugs with Questa” co-authored by me on this subject.

Drop in your questions and experiences with low power designs in the comment section or write to me at siddhakarana@gmail.com

Living the PRESENT - the current decade!

The present decade (2001-2010) witnessed the metamorphosis of verification domain from adoloscence to maturity. A lot of the initiatives from the last decade paid off well to scale verification along with the ASIC designs while a lot of new investments were made keeping the next decade in mind. Some verification features that made their mark in this decade include -

1. System Verilog - touted as a one stop solution for HDL+HVL, addressing the limitation of the designers using HDLs (Verilog/ VHDL) and the verification engineers debating on HVLs (e/Vera). An extension of Verilog 2005 and largely based on OpenVera language, System Verilog became a darling of everyone from the Semiconductors as well as the EDA companies.

2. Standardization of HVLs e & SV - System Verilog was adopted as IEEE Standard 1800-2005 and then merged with the Verilog IEEE 1394-2005, leading to IEEE Standard 1800-2009. 'e' language promoted by Verisity and bought by Cadence went ahead getting standardized as IEEE 1647-2006. 

3. CDV - Code coverage stagnated as a baseline for measuring verification progress & completeness. Functional coverage supported by the HVLs was able to put forward a different dimension and widely accepted. Assertion coverage though promising wasn't able to spread its wings wide enough, partly, since it was scenario focussed and partly because of ownership issues between design & verification teams. Even test planning evolved a lot with many tools now aiding in developing a robust test plan by keeping a track of architecture document and extending means for defining comprehensive coverage goals upfront.

4. Reusability - A jargon that still makes news every now & then. Design complexity jumping new heights and time to market panic lead to evolution of IP designs and reusability. With design, verification IPs also defined their market quite strongly. Methodologies (eRM & RVM) helped in packaging the verification environment so as to make it portable from module to chip level and between programs. SV evolution brought in OVM & VMM complementing eRM & RVM respectively. [Note - OVM is a mix of eRM & AVM]. Finally, this decade will commence with standardization of methodology - UVM.

5. AMS - The intricacies of Analog always kept it behind the digital world in terms advancements in process technologies or other methodologies. Product demands from various domains lead to single chip (packaging) and later single die solutions. Since analog & digital designers were always alien to each other these integrated designs demanded verification. AMS simulations addressed this space with various schemes like - Gate level representation of digital & transistor level representation of analog, Gate level or RTL representation of digital & behavioral modeling of the analog etc.

6. Formal verification - Directed verification opened gates to constrained random verification (CRV) where unforseen scenario generation was the focus. Given time & compute resource limitations CRV struggled to reach all possible points in the designs in a defined time. Formal approach proposes to resolve these limitations. However, slow advancement on the simulators limited the adoption of this methodology for most part of the decade.

7. Low power verification - Area and performance had been defining ASIC designs until power became an important measure. Innovative design techniques reduced power consumption with an overhead logic. EDA tools capable of verifying power aware designs - MVSIM & MVRC from Archpro (later acquired by Synopsys) and Cadence IUS & Conformal LP did quite well to address this issue. UPF & CPF emerged as two power formats that rushed to address representation of power aware designs. [UPF - IEEE 1801-2009].
 
8. Hardware accelerators - More gates, big designs, long simulation run time = bottleneck to tapeout in time. Next generation of hardware accelarators paved way for reducing the simulation turn around time. These boxes soon took shape of a complete platform for verification of the whole system and further advanced to help simulate some real time data into the designs before tapeout with much ease.

9. HW SW co-verification - With design focus shifting from the ASIC to SOC, system design & modelling became all the more important. Software testing became the next chokepoint for time to market. A well defined platform where software design & testing could start in parallel to the ASIC design came forefront. Better HW SW partioning, performance checks, system design issues etc all were well addressed with this platform.

10. Courses in verification - VLSI course became more prominent and adopted in almost all electrical & electronics courses. Late in the decade a need for focussed verification courses took centre stage. Many institutes delivering these courses addressed the need for a competent verification work force.

Next -
'Predictions for future - the next decade!'

Previous -
'Recap from the past - the last decade!'