Sunday, December 28, 2014

Top 10 DV events of 2014


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The semiconductor industry while growing at a modest rate is at crossroads to define the next killer category of products. The growth in the phone and tablet segment is bound to follow the footsteps of PC industry. IoT (Internet of Things) has been the buzzword but clear definition of the road map is still fuzzy. Infrastructure as always would continue to grow due to the insatiable appetite for faster connectivity and explosion in the amount of data coming in with cloud computing. Irrespective of the product definitions the need for increased functionality on smaller die size with low power and faster time to market at low cost would prevail. To respond to this demand, the DV community has been gearing up in small steps and some of those important ones were taken in 2014. As the stage is getting ready to bid farewell to 2014 and welcome the New Year, let’s have a quick recap of these events in no particular order –

1. UVM 1.2 - A final version of Universal Verification Methodology, was released by Accellera for public review before taking it forward for IEEE standardization. This finally marks an end to the methodology war and resulting confusion. 

2. PSPWG – While UVM has been an anchor for IP verification and reuse, verification of complex scenarios at SoC level is still a challenge particularly when multiple processors are involved and we are looking for reuse across compute platforms. Portable Stimulus Proposed Working Group kicked off this year bringing in stakeholders across the industry to brainstorm on a Unified Portable Stimulus definition as a potential answer to the SoC verification challenge.

3. Formal – Cadence buys Jasper for $170m claiming the largest formal R&D team on the planet. It is expected to help the customers further wherein integration of best of formal technologies from either side would combine and complement the simulation and emulation platforms. 

4. Verification Cockpit – Another interesting shift seen with major EDA vendors is pulling all verification solutions under one umbrella. This includes simulation, emulation, prototyping, formal, coverage, debug and VIPs etc. This is an important step for future SoCs wherein the DV engineer can use the best solution for a given problem to achieve faster verification sign-off.

5. Emulation – The wait was finally over where emulation solutions found wide adoption across the industry. This year witnessed that emulation is no more a luxury but a necessity to meet product schedule by accelerating verification turnaround and enabling the shift left in the product development cycle.  

6. DVCON – This year marked another milestone where in DVCON expanded its reach with Accellera sponsoring DVCON India and DVCON Europe providing an excellent platform for engineers to connect and share their experiments and experiences.

7. AMS – Mentor Graphics acquired Berkeley Design Automation, Inc., bringing in the required flow addressing analog, mixed-signal, and RF circuit verification.  This move is a step to integrate a fairly focused solution with the existing expertise at Mentor to address the next generation verification challenges that would unfold as analog claims more % on silicon. 

8. VIP – This year going with VIP solutions was a no brainer. The pitch of buy vs sell is long gone and industry has embraced third party VIPs with open arms. For a change, non occurrence of any major event in VIP domain was itself an event!

9. X prop – Another solution in verification that created much steam is the X-prop solution from all vendors to enable weeding out the functional X-s from the design at RTL level. This helped many projects reduce the turnaround time spent with GLS.

10. Standards Accellera announced revision of few other standards that include SystemC core language (SystemC 2.3.1) an update to the standard released in 2011 focusing on transaction level modelling, SystemC verification library (SCV 2.0) containing implementation of the verification extensions and Verilog-AMS 2.4 that includes extensions to benefit verification, behavioral modelling and compact modelling.

I hope you had an eventful 2014 with different tools, flows and methodologies. Drop in a comment with what you felt was most interesting in 2014 as we welcome 2015 and the events that would unfold with time.

Wish you all a Happy and Eventful 2015!

2 comments:

  1. Great list of Top 10 DV events of 2014 my friend that you had shared here on this blog. Truly I had great year 2014 and I wish I would attend number of NY events in 2015 also. Do you have a list of 2015 events too?

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  2. Nice post, thanks for sharing. I am looking for the GATE academy pune and I came across your blog.

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