tag:blogger.com,1999:blog-91572064051788430962024-03-07T09:04:13.845+05:30siddhakaranaNo boundaries...no restrictions...no constraints... randomly exploring Verification (sid'dha-karana) with Gaurav JalanGaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.comBlogger83125tag:blogger.com,1999:blog-9157206405178843096.post-28799788165982873072019-02-22T23:32:00.000+05:302019-02-22T23:32:38.605+05:30Quick chat with Tom Fitzpatrick : recipient of Accellera Technical Excellence Award<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-family: Verdana, sans-serif;"><span style="margin: 0px;">Moore’s law, the driving force behind
the evolution of the semiconductor industry, talks about the outcome wherein
the complexity on silicon doubles every 2 years. However, to achieve this
outcome for past 50+ years, several enablers had to evolve at the same or much
faster pace. Verification as a practice, unfolded, as part of this journey and
entered mainstream, maturing with every new technology node. To turn the wheel
around everytime, various spokes in the form of languages, EDA tools, flows,
methodologies, formats, & platforms get introduced. This requires countless
hours of contribution from individuals representing diverse set of
organizations & cultures putting the canvas together for us to paint the
picture. </span></span></div>
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<tr><td class="tr-caption" style="text-align: center;"><i><span style="font-family: Verdana, sans-serif; font-size: xx-small;">Tom Fitzpatrick</span></i></td></tr>
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<span style="font-family: Verdana, sans-serif;"><span lang="EN-US" style="margin: 0px;">At <a href="https://dvcon.org/">DVCon</a>, <a href="https://accellera.org/">Accellera</a> recognizes outstanding achievement of an individual and his/her contributions to the development of Standards. This year, Tom Fitzpatrick, Vice Chair of the Portable Stimulus Working
Group and member of the UVM Working Group, is the recipient of the <span style="color: #ffd966;">8<sup>th</sup>
annual Accellera Technical Excellence Award</span>. Tom who represents <a href="https://www.mentor.com/">Mentor</a> at
Accellera, has more than 3 decades of rich experience in this industry. In
a quick chat with us, he shares his journey as a verification engineer,
technologist & evangelist!!!</span><span lang="EN-US" style="margin: 0px;"> </span><span style="margin: 0px;"><span style="margin: 0px;"> </span><span style="margin: 0px;"> </span></span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">Many congratulations Tom! Tell us
about yourself & how did you start into verification domain?</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">Thanks! I started my career as a chip
designer at Digital Equipment Corporation after graduating from MIT. During my
time there, I was the stereotypical “design engineer doing verification,” and
learned a fair amount about the EDA tools, including developing rather strong
opinions about what tools ought to be able to do and not do. After a brief
stint at a startup, I worked for a while as a verification consultant and then
moved into EDA at Cadence. It was in working on the rollout of NC-Verilog that
I really internalized the idea that <span style="color: #ffe599;">verification productivity is not the same
thing as simulator performance</span>. That idea is what has really driven me over the
years in trying to come up with new ways to make the task of verification more
efficient and comprehensive.</span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">Great! You have witnessed verification
evolving over decades. How has been your experience on this journey? </span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">I’m really fortunate to have “grown
up” with the industry over the years, going from schematics and vectors to
where we are now. I had the good fortune to do my Master’s thesis while working
at Tektronix, being mentored by perhaps the most brilliant engineer I have ever
known. I remember the board he was working on at the time, which had both TTL
and ECL components, multiple clock domains, including a voltage-controlled
oscillator and phase-locked loop, and he got the whole thing running on the
first pass doing all of the “simulation” and timing analysis by hand on paper.
That taught me that even </span><span style="color: #ffe599; font-family: Verdana, sans-serif;">as we’ve moved up in abstraction in both hardware and
verification, if you lose sight of what the system is actually going to do, no
amount of debug or fancy programming is going to help you.</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">For me, personally, I think the
biggest evolution in my career was joining Co-Design Automation and being part
of the team that developed SUPERLOG, the language that eventually became
System Verilog. Not only did I learn a tremendous amount from luminaries like
Phil Moorby and Peter Flake, but the company really gave me the opportunity to
become an industry evangelist for leading-edge verification. That led to
working on VMM with Janick Bergeron at Synopsys and then becoming one of the
original developers of AVM and later OVM and UVM at Mentor. From there I’ve
moved on to Portable Test and Stimulus as well.</span></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;"><span style="margin: 0px;">So, what according to you were key
changes that have impacted verification domain the most?</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">I think there were several. The
biggest change was probably the introduction of <a href="http://whatisverification.blogspot.com/2013/05/constrained-random-verification-flow.html">constrained-random</a> stimulus and
functional coverage in tools like Specman and Vera. Combined with concepts like
object-oriented programming, these really brought verification into the
software domain where you could model things like the user accidentally
pressing multiple buttons simultaneously and other things that the designer
didn’t originally think would happen. I think it was huge for the industry to
standardize on UVM, which codified those capabilities in System Verilog so users
were no longer tied to those proprietary solutions and the fact that UVM is now
the dominant methodology in the industry bears that out. As designs have become
so much more complex, including having so much software content, I hope that
</span><span style="color: #ffe599; font-family: Verdana, sans-serif;">Portable Stimulus will serve as the next catalyst to grow verification
productivity.</span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">Tom, you have been associated with
Accellera for long & contributing to multiple standards in different
capacities. How has been your experience working on standards?</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">My experience with standards has
been entirely self-inflicted. It started when I was at Cadence and heard about a
committee standardizing Verilog but that there were no Cadence people on the
committee. I kind of joined by default, but it’s turned out to be a huge part
of my career. Aside from meeting wonderful people like Cliff Cummings, Stu
Sutherland and Dennis Brophy, my work on standards over the years has given me
some unique insights into EDA tools too. I’ve always tried to balance my “user
side,” where I want the standard to be something I could understand and use,
with my “business side,” where I have to make sure that the standard is
supportable by my company, so I’ve had to learn a lot more than someone in my
position otherwise might about how the different simulators and other tools
actually work. On a more practical note, working on standards committees has
also helped me learn everything from object-oriented programming to Robert’s
Rules of Order.</span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">You have been one of the key drivers
behind development of Portable Test and Stimulus Standard (PSS). How was your
experience working on this standard compared to UVM?</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">Good question! UVM was much more of
an exercise in turning existing technology into an industry standard, which
involved getting buy-in from other stakeholders, including ultimately VMM
advocates, but we didn’t really do a whole lot of “inventing.” That all
happened mostly between Mentor and Cadence in developing the OVM originally. We
also managed to bring most of the VMM Register Abstraction Layer (RAL) into UVM
a bit later.</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">Portable Stimulus has been different for
two reasons. First, I’m the vice-chair of the Working Group, so I’ve had to do
a lot more planning than I did for UVM. The other is that, since the technology
is relatively new, we had the challenge of combining the disparate capabilities
and languages used by existing tools into a new declarative language that has
different requirements from a procedural language like System Verilog. We spent
a lot of time debating whether the standard should include a new language or
whether we should just use a C++ library. It took some diplomacy, but we
finally agreed to the compromise of defining the new language and semantics,
and then producing a C++ library that could be used to create a model with the
same semantics. To be honest, we could have played hardball and forced a vote
to pick only one or the other, but we wanted to keep everyone on board. Since
we made that decision, the working group has done a lot of really great work.</span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">What are the top 2-3 challenges
that you observe we as an industry need to solve in verification domain?</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">Remember when I said earlier that
verification productivity is about more than simulator performance? Well, with
designs as big and involved as they are today – and only going to get more so –
we’re back at the point where you need a minimum amount of performance just to
be able to simulate the designs to take advantage of things like UVM or
Portable Stimulus without it taking days. This is actually part of the value of
Portable Stimulus in that the engine can now be an emulator, FPGA prototype or
even silicon and you can get both the performance to get results relatively
quickly and the productivity as well.</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">The other big challenge I think is
going to be increasing software content of designs. Back when I started,
“embedded software” meant setting up the hardware registers and then letting
the hardware do its thing. It made verification relatively easy because RTL
represents physical hardware, which doesn’t spontaneously appear and disappear,
like software. We’ve spent the last ten or so years learning how to use
software techniques in verification to model the messy stuff that happens in
the real world and making sure that the hardware would still operate correctly.
When you start trying to verify a system that has software that could
spontaneously spawn multiple threads to make something happen, it becomes much
harder. Trying to get a handle on that for debug and other analysis is going to
be a challenge.</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">But perhaps the biggest challenge is
going to be just handling the huge amounts of data and scenarios that are going
to have to be modelled. Think about an autonomous car, and all of the
electronics that are going to have to be verified in an environment that needs
to model lots of other cars, pedestrians, road hazards and tons of other stuff.
When I let myself think about that, it seems like that could be a larger leap
than we’ve made since I was still doing schematic capture and simulating with
vectors. I continue to be blessed to now work for a company like <a href="https://www.mentor.com/">Siemens</a>, that
is actively engaging this very problem.</span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">Based on your vast experience, any
words of wisdom to the practicing & aspiring verification engineers?</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;">I used to work with a QA engineer
who was great at finding bugs in our software. Whenever a new tool or user
interface feature came out, he would always find bugs in it. When I asked him
how he did it, he said he would <span style="color: #ffe599;">try to find scenarios that the designer
probably hadn’t thought about</span>. That’s pretty much what verification is. Most
design engineers are good enough that they can design a system to do the
specific things they think about, even specific corner cases. But they can’t
think of everything, especially with today’s (and tomorrow’s) designs.
Unfortunately, if it’s hard for the design engineer to think of, it’s probably
hard for the verification engineer to think of too. That’s why verification has
become a software problem – because that’s the only way to create those
unthought-of scenarios. </span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;"><span style="color: #f1c232;">Thank you Tom for sharing insights
& your thoughts.<span style="margin: 0px;"> </span></span></span></span></div>
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<span style="margin: 0px;"><span style="color: #f1c232; font-family: Verdana, sans-serif;">Many congratulations once again!!!</span></span></div>
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<span style="margin: 0px;"><span style="font-family: Verdana, sans-serif;"><a href="https://dvcon.org/">DVCon US 2019</a> - February 25-28, 2019 - Double Tree Hotel, San Jose, CA</span></span></div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com2tag:blogger.com,1999:blog-9157206405178843096.post-38595613374145992018-11-06T14:35:00.000+05:302018-11-06T14:35:14.224+05:30Quick chat with Srini Maddali : Keynote speaker Accellera Day India 2018<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-family: Verdana, sans-serif;">Distant communication has come a long way over the last century!
The 64 kbps telephone line enabling <span style="color: #ffd966;">real time communication</span> revolutionized traditional
messenger based means. Wireless communication brought in another revolution
enabling people to talk <span style="color: #ffd966;">on the go</span><span style="color: #ffd966;">!</span> While this eased up communication, it also took
technology to remote places adding millions of users to this network. With
wireless & internet joining hands, a <span style="color: #ffd966;">new world of possibilities</span> opened up that
continues to evolve and amaze us by the day! <a href="https://www.qualcomm.com/">Qualcomm</a> continues to lead the effort of
bringing wireless technology and associated enablers to mainstream. The
verification team at Qualcomm works relentlessly to defy the challenges posed
by this accelerated rise in complexity every day. As we look forward for the 5G enabled
world, what are some of these challenges & expectations from the next
generation of verification tools & technologies?</span></div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVpPtdXKbzfv17qkRgVnDjB96QFHZFNhQqydpiRNaUUVJRSsNtIGG1CbAvBD8rr4EP9QYFM4GkAENr-3kxeelJ1Z-5GaKs1Pq9-567Fj6m08bC0BBGJzQYL07RT3rF1vYDCpInvABpMVI/s1600/Srini2.png" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" data-original-height="872" data-original-width="685" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiVpPtdXKbzfv17qkRgVnDjB96QFHZFNhQqydpiRNaUUVJRSsNtIGG1CbAvBD8rr4EP9QYFM4GkAENr-3kxeelJ1Z-5GaKs1Pq9-567Fj6m08bC0BBGJzQYL07RT3rF1vYDCpInvABpMVI/s200/Srini2.png" width="156" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i><span style="font-family: Verdana, sans-serif;">Srini Maddali</span></i></td></tr>
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<i></i><span style="font-family: Verdana, sans-serif;"></span><br /></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh77G_Rvm8roxuMjbdDWb1swj1CVb-RXVfk-Cyg1tTDQCOcTuBSYiBSnM9oXEAhrcq9-irU10I9xYJyaptBZ-dtD3GZUC5ETPvjSe5QmdZ163HqvkrTATmrZRyv9IUsTgjbPeHE4OyLB54/s1600/SriniMPhoto-2.jpg" imageanchor="1" style="clear: right; float: right; margin-bottom: 1em; margin-left: 1em;"></a><span style="font-family: Verdana, sans-serif;">Srini Maddali, Vice President, Technology at <a href="https://www.qualcomm.com/">Qualcomm</a>
India Design Center leads the Mobile SoC development Engineering teams. With
focus on <span style="color: #ffd966;">Low-Power, High-Performance SoC design and enabling rapid ramp to
volume</span> of these designs, Srini has a first-hand information on these challenges
which he would be sharing as part of his <span style="color: #ffd966;">keynote</span> on the <a href="http://accellera.org/news/events/accellera-day-india-2018">Accellera Day</a> in India
at Radisson Blu Bengaluru on <a href="http://www.accellera.org/news/events/accellera-day-india-2018/accellera-day-india-registration">November 14, 2018</a>. A quick chat with Srini
unfolded the adventurous ride that awaits the verification community as we
embrace proliferation of IoT through the 5G route. Read on!!!</span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">Srini, you plan to discuss on the topic “Challenges in
Validation of Low Power, High Performance, and Complex SoCs at Optimal Cost”?
Tell us more about it?</span></div>
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<span style="font-family: Verdana, sans-serif;">Year over Year, complexity, performance and power
requirements have been increasing rather drastically. In addition to that, time
from the start of SoC development to customer deployment is shrinking. These
pose significant challenges to SoC development teams both in design and
validation. </span></div>
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<span style="font-family: Verdana, sans-serif;">For our team to put a test plan comprehending each use
case requirements of each domain in these Systems (System that is on a monolithic
die) and then validate concurrent use cases involving multiple domains
operating independently, creating conditions that would stress the designs is quite
challenging. On top of this, the team must validate performance aspect of each
domain independently, valid concurrent scenarios, and simulate use cases beyond
the spec of system ensuring graceful exit each time. </span></div>
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</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The challenges further become multi-fold when simulating
power profiles comprising number of power domains with huge number of system
use cases interacting dynamically.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The Cost aspect is beyond the resource aspect and instead
the Time aspect of delivering SoC to customer on a tight schedule.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Combining all of these with multiple SoCs getting
developed in parallel to leverage the best across the chips and validating
entire SoC builds up a multi-dimensional challenge for any team. </span><span style="font-family: Verdana, sans-serif;">As part of the team, I witness this with every chip
development and multiple developments per year. I would be covering these aspects in my
talk.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">WoW!!! Srini, you are throwing light on the whole
iceberg! Wondering how has been your team’s experience with the philosophy that
verification takes 70% of the design cycle? </span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">As mentioned, with the design complexities and to
validate the system use cases, verification effort starts from the architecture
phase of the design till customer sampling. Teams engaging right from the
architectural level discussion helps to define the test plans, defining task
details and prioritizing tasks covering all aspects of system validation i.e.
functional, performance, power, etc. On top of this, our teams leverage Formal
and emulation platforms to cover any gaps in the coverage.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Srini you mentioned leveraging Formal technology. Has it been
offloading simulation tasks or trailblazing verification?</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Formal has been an integral part of our verification
methodology and our teams leverage its capability in validating our designs/IPs
and SoCs. We use Formal right from providing jumpstart to design validation
before deploying UVM or other techniques till the last mile of coverage closure.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">UVM as a methodology was proposed to solve some of these
challenges for IP level & aid at SoC level too. How does your team views
UVM’s contribution in alleviating these challenges?</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">With the challenges described, creating verification
environment for every SoC is very difficult and inefficient. Having modular
verification environment that enables to port IP/Design to SoC and re-use
across SoCs/designs helps to improve efficiency and quality. UVM enabled to
scale this to our need and certainly helped alleviating the challenges handling
the complexity as well as managing multiple SoC developments. UVM has been serving very well to the complexities of last multiple years. With
Designs/SoCs becoming more-and-more complex managing it with UVM TB is itself becoming a challenge.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Srini you also mentioned using emulation. How has been
your team’s experience with this platform?</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">With the number of clock domains, power domains, and infra
systems, some designs can be bit tight for emulation platforms. Based on the
need and complexity we deploy all techniques including hybrid emulation to
cover the SoC.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">A lot of these challenges can be subsided with an
integrated holistic approach to verification & validation. Do you believe
Portable Stimulus aiming in those lines would provide a solution to them?</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Yes, with Portable Test & Stimulus, once the vendor
tools start supporting full feature set as defined in the standard, it shall
enable validation at context level extending the ability to leverage block/IP
level validation at the system level. This will help to cover system level scenarios
effectively and get the coverage at context and use case level. </span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Qualcomm is a pioneer in cellular technology. 5G would
enable a system of systems across all domains. Do you observe Safety &
Security as next set of challenges already standing outside the door?</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Safety & Security is always a challenge with constant
news about vulnerabilities detected in the systems. With 5G, we will have
systems that can operate differently based on the use case/environment e.g. Streaming
movie or video would be a high bandwidth mode vs Automotive environment that operate
in very low latency and guaranteed service vs AI mode leveraging cloud compute
and so on. Security and safety will be even more critical for systems that
morph based on the need/environment. It is very interesting and equally challenging
topic for sure.</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Srini, this year we are having Accellera Day for the
first time in India. What are your expectations from the event?</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="text-align: justify;">
</div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;">It is indeed nice to see. Having such events help the
VLSI community to come together, share their ideas, views and learn about the latest
trends in the vast Verification universe.</span></div>
<div style="margin: 0px; text-align: justify;">
<br /></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Thank you Srini!</span></div>
<div style="margin: 0px; text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div style="margin: 0px; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><a href="http://accellera.org/news/events/accellera-day-india-2018">Accellera Day India 2018</a> is getting hosted at Radisson Blu, Bangalore on 14th November 2018. <a href="http://www.accellera.org/news/events/accellera-day-india-2018/accellera-day-india-registration">Register now!!!</a></span></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com1tag:blogger.com,1999:blog-9157206405178843096.post-75832688300126721642018-03-19T00:36:00.000+05:302018-03-19T06:46:14.099+05:30Negative Testing in functional verification!!!<div dir="ltr" style="text-align: left;" trbidi="on">
<br />
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Imagine someone on an important call and the mobile device reboots suddenly! The call was to inform that the devices installed at the
smart home seems to be behaving erratically with only elderly parents &
kids to provide any further details. On booting up, the smartphone flashes that
there has been a security breach and data privacy has been compromised. Amidst this
chaos, the car’s cruise control didn’t respond to pressing of the pedals!!!
Whew!!!.... nothing but one of the worst nightmares in the age of technology we
live in! But what if some of it could be true someday? What if the user has
little or no idea about that technology? <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">The mobile revolution has enabled a common man to access
technology and use it for different applications. The data from <a href="https://www.internetworldstats.com/emarketing.htm">Internet world statistics </a>suggest that internet adoption worldwide has increased from 0.4% of
world population in 1995 to 54.4% in 2017. Related data also indicate that a sizable
portion of the users are aged & illiterate. The ease of use has potentially
driven this adoption further with the basic assumption that devices would be functioning correctly
24x7 even if used incorrectly out of ignorance. The same assumptions are seamlessly getting
extended to safety critical domains such as Medical & Auto introducing
several unknown risks for the user.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">So how does this impact the way we verify our designs?</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Traditionally, verification is assumed to be ensuring that
the RTL is an exact representation of the specifications. Given that the state
space based on the design elements is so very huge, a targeted verification
approach covering positive verification has been in practice all throughout. Here,
<a href="http://whatisverification.blogspot.in/2010/10/proof-of-no-bug-or-no-proof-of-bug.html">Proof of no bug is assumed to be equal to No proof of bug!</a> The only traces of
anything beyond this approach include – <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">- Introducing asynchronous reset during the test execution to
check that the design boots up correctly again.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">- Introducing stimulus triggering exceptions in the design.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">- Simulating architecture or design deadlock scenarios.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">- Playing around with key signals per clock for low power
scenarios and reviewing the corresponding design response.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<br />
<div class="MsoNormal" style="text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhy8Tj-aazQRljOy8ojc2stcQnu2vX-XkEUkSyxEANS6n9jmhLtpfkAHjFcsJApJVoCSyGTn2V3Pa35crgk01plNTNTEiKcpYfgwuHCuxJDMvsb2BTeR3zsi8g8j2HJXh2ywURLt8_XNF8/s1600/Donkey-Pulling-a-Heavy-Cart-47611.jpg" imageanchor="1" style="clear: left; display: inline !important; float: left; margin-bottom: 1em; margin-right: 1em; text-align: center;"><img border="0" data-original-height="664" data-original-width="1000" height="132" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhy8Tj-aazQRljOy8ojc2stcQnu2vX-XkEUkSyxEANS6n9jmhLtpfkAHjFcsJApJVoCSyGTn2V3Pa35crgk01plNTNTEiKcpYfgwuHCuxJDMvsb2BTeR3zsi8g8j2HJXh2ywURLt8_XNF8/s200/Donkey-Pulling-a-Heavy-Cart-47611.jpg" width="200" /></a><span style="font-family: "verdana" , sans-serif;">But as we move forward with security
and safety becoming key requirements of the design, </span><span style="font-family: "verdana" , sans-serif;">is this good enough</span><span style="font-family: "verdana" , sans-serif;">? There is a clear need to redefine
the existing approach and bring <b><span style="color: #f1c232;">Negative testing</span></b> to mainstream! </span><span style="font-family: "verdana" , sans-serif;">Negative testing ensures that the design can gracefully
handle invalid inputs, unexpected user behavior, potential security threats or defects
such as structural faults introduced while the device is operational. Amidst
shrinking design schedules, negative testing really requires creative thinking coupled
with focused effort. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">To start with, it is important to question the assumptions
used while defining the verification plan for the design. Validating those
assumptions itself can lead to a set of scenarios to be verified under this
category. Next, review the constraints applied while generating stimulus to
list out potential illegal inputs of interest. Caution should be taken in defining
this list as the state space would be large. Reviewing it in the context (</span><a href="http://whatisverification.blogspot.in/2014/10/moving-towards-context-aware.html" style="font-family: Verdana, sans-serif;">Context Aware Verification</a><span style="font-family: "verdana" , sans-serif;">) of end application would surely help in narrowing down this
illegal stimulus set. Further to this, faults need to be injected at critical points inside the DUT using EDA tools or innovative testbench
techniques. This is important for safety critical applications where the design
needs to respond to random faults and exit properly while notifying about the
fault or even correct it. Of course not to forget that appropriate coverage needs to be applied to measure the reach of this additional effort.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">As we step into an era of billions of devices empowering
humans further, it is crucial that this system of systems is defect free especially
when it touches safety critical part of our life. Negative testing is a
potential way forward ensuring reliability of designs for such applications. As
is always said – </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: center;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;"><i>Better safe than sorry! <o:p></o:p></i></span></div>
<div class="MsoNormal" style="text-align: center;">
<br /></div>
<div style="text-align: justify;">
<br /></div>
</div>
<div class="blogger-post-footer"><a href="https://twitter.com/share" class="twitter-share-button" data-via="gjalan">Tweet</a>
<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com4tag:blogger.com,1999:blog-9157206405178843096.post-40162390852474785402018-03-04T18:41:00.001+05:302018-03-04T18:41:53.218+05:30Portable Stimulus : redefining verification play field yet again!<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">In the last <a href="http://whatisverification.blogspot.in/2010/09/recap-from-past-last-decade.html">3+ decades</a>, verification has come a long way! Right
from quick testing by designers to dedicated verification teams moving from <a href="http://whatisverification.blogspot.in/2012/12/evolution-of-test-bench-part-1.html">directed testing</a> to <a href="http://whatisverification.blogspot.in/2013/01/evolution-of-test-bench-part-2.html">constrained random</a> and adding elements of formal apps at times, it has been an eventful journey! <a href="http://whatisverification.blogspot.in/2011/03/uvm-redefining-verification-play-field.html">Standardization</a> of UVM enabled a common framework with which the fraternity marched forward in sync with each other. Horizontal reuse viz. at the IP level experienced maximum benefits
of UVM while vertical resume viz. from
IP to SoC level observed limited returns. Apart from the methodology, verification
has also proliferated beyond simulation or emulation into virtual prototyping, FPGA
validation, post silicon functional validation & HW SW co-verification. Today,
the reuse aspects are not limited from IP to SoC or across projects but between platforms too. It is extremely important to realize reuse of efforts at any level across different
vehicles enabling first silicon success. The challenge however is that each of
these vehicles involve multiple stakeholders like architects (Chip , SW,
system), SystemC modelling engineers, RTL designers, verification engineers, prototyping
experts, post silicon debuggers and SW developers, each defining & driving
the stages of SoC design cycle. Different goals focusing on a specific stage, different
approaches in solving these problems and different means of representing solutions
has made the task of reuse across the platforms – a convoluted puzzle!!!<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjIy1v1bg2UiC3li9bo2-tLvCc2ES7RihaYFhqIoabfz2N0FP9VZ6WTSlFL9hFxR4q8b9fQ_FI8FzGo6ovwCToXm-ECG8OoQP1FCTda9Ju5ma6XxL0mLrM3VQqR93_ssz-D0dpNvPcAMaw/s1600/logo-portable-stimulus-200.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" data-original-height="95" data-original-width="200" height="95" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjIy1v1bg2UiC3li9bo2-tLvCc2ES7RihaYFhqIoabfz2N0FP9VZ6WTSlFL9hFxR4q8b9fQ_FI8FzGo6ovwCToXm-ECG8OoQP1FCTda9Ju5ma6XxL0mLrM3VQqR93_ssz-D0dpNvPcAMaw/s200/logo-portable-stimulus-200.png" width="200" /></a><span style="font-family: Verdana, sans-serif;">To solve this problem, <a href="http://accellera.org/">Accellera</a> initiated a task force
called <a href="http://accellera.org/activities/working-groups/portable-stimulus">Portable Stimulus Working Group </a>(PSWG) that reviewed the concern &
potential solutions. After long & regular sessions of intense activity in
last couple of years, the group has come up with a proposal in form of a
standard. Beta release of the preliminary
version of the Portable Test and Stimulus Standard is now opened for public review.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The basis of the solution relies upon taking the stimulus
definition across platforms to an <span style="color: #f1c232;">abstraction layer</span> where the focus is on <span style="color: #f1c232;">what
is needed</span> instead of <span style="color: #f1c232;">how it shall be implemented</span>? The idea is to understand
& represent the <span style="color: #f1c232;">action/outcome</span> i.e. the behavior of the DUT when the test runs.
While representing these actions, the focus would be on what would be the
inputs and outputs, what resources are required in the DUT, and their relationship with each other? The how part i.e. the implementation will
be left to a <span style="color: #f1c232;">hidden layer</span> (read EDA tool) to generate the required stimulus for
the target platform based on the scenario definition. The actions referred above are all declarative and not procedural or executable by themselves. A set
of these static actions can be used to construct a scenario, analyzed for
coverage to determine the paths to be traversed & dumped into a test format
using the hidden layer. <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">To represent these actions, the PSWG has proposed 2 formats -
<span style="color: #f1c232;">Domain Specific Language (DSL)</span> that is close to System Verilog and a <span style="color: #f1c232;">restricted C++
library</span>. Both these formats have equivalent semantics that are completely
interchangeable such that for each line in the DSL there is an exactly equivalent
C++ library entry. If one defines the actions of an IP in DSL and another
IP in C++ library, both can be read together to generate a SoC level scenario for the
target platform.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">While the road of moving from developing each testcase to a testbench
that generates tests has been long, it’s time to take another step in the direction of standardizing the <span style="color: #f1c232;">stimuli!</span>
This would feed the testbenches for IP/SoC verification & be reused by other
<a href="http://whatisverification.blogspot.in/2015/10/the-magical-chariot-in-verification.html">workhorses</a> of verification & validation in the SoC design cycle. Remember, <span style="color: #f1c232;">reuse</span> is one of the keys to keep up with <a href="http://whatisverification.blogspot.in/2015/04/moores-law-journey-of-50-years.html">Moore's law</a>!!!<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The public review period for this proposal is open until
Friday, March 30, 2018. </span><a href="http://accellera.org/images/downloads/drafts-review/PSS_EAII_Feb_28_2018_Public_Review.pdf" style="font-family: Verdana, sans-serif;">Download</a><span style="font-family: Verdana, sans-serif;"> & </span><a href="http://forums.accellera.org/forum/40-portable-stimulus-discussion/" style="font-family: Verdana, sans-serif;">review </a><span style="font-family: Verdana, sans-serif;">NOW!!!</span></div>
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<div class="blogger-post-footer"><a href="https://twitter.com/share" class="twitter-share-button" data-via="gjalan">Tweet</a>
<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com2tag:blogger.com,1999:blog-9157206405178843096.post-48810579704140945992018-02-18T13:00:00.002+05:302018-02-18T13:00:29.178+05:30Moana of Verification!!!<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-family: Verdana, sans-serif;">Dear Readers!!!! Welcome back!!!<o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">During this lull period of sharing thoughts, I realized
that even blogging faces the same dilemma of verification on “How much is
enough”. Finally, as a verification engineer should think, I decided to
continue as much as I can with the hope to improve blogging frequency than
before – wish there was <a href="http://whatisverification.blogspot.in/2015/04/moores-law-journey-of-50-years.html">Moore’s law</a> for
bloggers too <span style="color: #f1c232;">😊</span>!!! Since this is the first one of this year
(Happy New year folks!!!) & by this time of the year the intent, action and
discussions on new year resolutions would have died down mostly, let’s start
from there. While speaking to budding DV
engineers on their new year resolutions around verification, I discovered that
somehow focus on the end goal is missing & they seem to be trending into
all directions. </span><span style="font-family: Verdana, sans-serif;">Reason? Well! Possibly many –</span></div>
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<span style="font-family: Verdana, sans-serif;">- The never ending gap between industry expectations &
Academia.<o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">- Missing core elements in the Job description of a
verification engineers.<o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">- Overwhelming solutions that enable verification….. etc.<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: Verdana, sans-serif;">Still confused on what I mean? Let me explain!<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: Verdana, sans-serif;">When I started my career as a verification engineer with
legacy directed verification approaches, all I learnt was that, to be
successful you need to have - <span style="color: #f1c232;">a Nose for Bugs!</span> In a way, that was also
because one needed to maximize returns from each test so, you handcraft each one to
really mine bugs. With rising silicon complexity, verification domain has been
experiencing consistent advancements enabling us verify designs faster & better.
During this shift, the expectations from verification engineers also kept
changing i.e. demanding experience on new flow, language or methodology. The rise
of SV & UVM further accelerated this shift giving a taste of elaborate
& sometimes exotic code development opportunities for the DV engineers.
While this continued, reuse gained momentum on the design & eventually on
verification too. Due to this the code development gave way to reuse & with
latest verification flow/methodologies, the verification engineers started
spending more time on derivative designs that demand debug capabilities over
development. <o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: Verdana, sans-serif;">Coming back to our budding engineers discussion, learning
a new flow/methodology would end up having expectations on development work
which may not really be needed always. This trend has often lead to the confusion of
multiple directions where the engineer ends up settling on the means losing focus on the end goal. As a DV engineer, our goal
is to find bugs! Approaches like Directed/Constrained Random/Formal or
languages, methodologies & platforms like simulator/emulator etc. are all
means to hunt bugs. While expertise in many or all of these are
important and occasionally may even lead to a career, the expectations from
verification engineer is really to catch bugs! <o:p></o:p></span></div>
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<br /></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjwo31jzinXJNuLSa9eAaHPbUAazXKDriggkr-0ua5THYgmJe8zR4m_HmTFfv1x12dpPAMOufA8LEEKiyWQXTI6DGSTx287pD2LABzcwe-hLaQjp-Cy-xuyDLMRjN4VcoPhDgqHzsYhxP0/s1600/movieposter.jpg" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" data-original-height="402" data-original-width="279" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjwo31jzinXJNuLSa9eAaHPbUAazXKDriggkr-0ua5THYgmJe8zR4m_HmTFfv1x12dpPAMOufA8LEEKiyWQXTI6DGSTx287pD2LABzcwe-hLaQjp-Cy-xuyDLMRjN4VcoPhDgqHzsYhxP0/s200/movieposter.jpg" width="138" /></a></div>
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<span style="font-family: Verdana, sans-serif;">How does this relate to the topic of the blog?<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: Verdana, sans-serif;">Well! Moana is a film on the story of a girl named Moana,
daughter of a chief of a Polynesian village.
She is chosen by the ocean to reunite a mystical relic with a goddess. When a blight strikes
her island, Moana sets sail in search of Maui, a legendary shapeshifting demigod,
in the hope of returning the heart of Te Fiti and saving her people. In this
journey of hers, she discovers that her tribe were ‘voyagers’ who have
forgotten their virtue and settled as villagers on an island which would die
down soon. She not only saves the island & her people but leads them back
to their original self – a journey which is more exciting & enriching!</span><o:p></o:p></div>
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<span style="font-family: Verdana, sans-serif;">Similarly, <a href="http://whatisverification.blogspot.in/2011/03/uvm-redefining-verification-play-field.html">UVM</a>, formal apps and <a href="http://whatisverification.blogspot.in/2015/10/the-magical-chariot-in-verification.html">emulation</a> etc. are all
means to find bugs in your verification journey. Don’t just settle for the
means which might be short-lived sometimes but shoot for the end goal & be the Moana of Verification!!! A worthy
resolution to pursue <span style="color: #f1c232;">😊</span>!!! </span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
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<span style="font-family: Verdana, sans-serif;">What was your resolution on verification on this New Year???</span></div>
</div>
<div class="blogger-post-footer"><a href="https://twitter.com/share" class="twitter-share-button" data-via="gjalan">Tweet</a>
<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com10tag:blogger.com,1999:blog-9157206405178843096.post-1219098876963312252017-09-10T13:52:00.000+05:302017-09-10T13:52:06.511+05:30Quick chat with Vishal Dhupar : Keynote speaker DVCon India 2017<div dir="ltr" style="text-align: left;" trbidi="on">
<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: right; margin-left: 1em; text-align: right;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6t9SLe0IwEDw6HlDXWn8tCi45TANud-yd-Lm0XVGIBXt7HxuGGKHrNEO_dve1UqO3rqQdtCdmFu2uxaWk0WSZjvuSgSdp1NFnPUXaZUoDQq6Egch-zih7kG8d1ac5tiOTYNmYTqgBt9A/s1600/82+-+Vishal+Dhupar.jpg" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" data-original-height="1200" data-original-width="800" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6t9SLe0IwEDw6HlDXWn8tCi45TANud-yd-Lm0XVGIBXt7HxuGGKHrNEO_dve1UqO3rqQdtCdmFu2uxaWk0WSZjvuSgSdp1NFnPUXaZUoDQq6Egch-zih7kG8d1ac5tiOTYNmYTqgBt9A/s200/82+-+Vishal+Dhupar.jpg" width="133" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i>Vishal Dhupar</i></td></tr>
</tbody></table>
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<span style="font-family: Verdana, sans-serif;">Imagine learning how to ride a bicycle! You learn to balance - pedal - ride on a straight line - turn - ride in busy streets - All set!!! It takes
step by step learning & then if you are offered a different bicycle you
would try to apply the “truths” you discovered in your earlier learning process &
quickly pick up the new one too. Our machines so far perform the tasks they are
programmed for and as obedient followers carry out the required job. However,
the new wave of technology is striving to make the machines more intelligent,
to not only seek but offer assistance, to make our decision making better, help
an ageing population store & retrieve memories that fade and much more!!!
Sounds interesting? Conniving? …??? <o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">Vishal Dhupar, Managing Director – Asia South at <a href="http://www.nvidia.com/">Nvidia</a>
would be discussing <span style="color: #f1c232;">Re-Emergence Of Artificial Intelligence Based On Deep
Learning Algorithm</span> as part of the <a href="https://dvcon-india.org/content/event-details?id=241--82">invited keynote</a> on Day 1 <a href="https://dvcon-india.org/">DVCon India</a>
2017. Passionate about the subject, Vishal shares the background & what
lies ahead for us in the domain of AI & Deep Learning. Extremely useful
from beginners to practitioners!!!<o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">Vishal your
keynote focusses on AI & Deep learning – intricate & interesting topic.
Tell us more about it?</span></div>
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<span style="font-family: Verdana, sans-serif;">Curiously,
the lack of a precise, universally accepted definition of AI probably has
helped the field to grow, blossom, and advance at an ever-accelerating pace.
Claims about the promise and peril of artificial intelligence are abundant, and
growing.<o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">Several
factors have fueled the AI revolution which will be the premise of my talk.
Touching upon how machine learning is maturing, and further being propelled
dramatically forward by <b>deep learning</b>, a form of adaptive artificial
neural networks. This leap in the performance of information processing
algorithms has been accompanied by significant progress in hardware and
software systems technology. Characterizing AI depends on the credit one is
willing to give synthesized software and hardware for functioning <b>appropriately</b> and
with <b>foresight</b>. I will be touching upon a few examples of AI
advancements.</span><span style="font-family: "Times New Roman",serif; mso-bidi-font-family: "Times New Roman"; mso-bidi-theme-font: minor-bidi; mso-fareast-font-family: "Times New Roman";"><o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">How do we
differentiate between machine learning, artificial intelligence & deep
learning?</span></div>
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<span style="font-family: Verdana, sans-serif;">Machine
learning, deep learning, and artificial intelligence all have relatively
specific meanings, but are often broadly used to refer to any sort of modern,
big-data related processing approach. You can think of deep learning,
machine learning and artificial intelligence as a set of concentric circles
nested within each other, beginning with the smallest and working out. Deep learning
is a subset of machine learning, which is a subset of AI. When applied to a
problem, each of these would take a slightly different approach and hence a
delta in the outcome.<o:p></o:p></span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgs7x1FOCERl3vS6UByrdAnMF9G-r0EtqwObhcZflGAEPVe0V9LyqR_BoUmcUYuOopzAEkrK1VPpyuNIrXiQdpsYmSlTDhbDUXnfi9muhcPbnRiVm3GpOJgvIGxxQ8sNXhtoUi5VqmFiFk/s1600/1.png" imageanchor="1" style="clear: left; display: inline !important; margin-bottom: 1em; margin-right: 1em; text-align: center;"><img border="0" data-original-height="687" data-original-width="1080" height="404" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgs7x1FOCERl3vS6UByrdAnMF9G-r0EtqwObhcZflGAEPVe0V9LyqR_BoUmcUYuOopzAEkrK1VPpyuNIrXiQdpsYmSlTDhbDUXnfi9muhcPbnRiVm3GpOJgvIGxxQ8sNXhtoUi5VqmFiFk/s640/1.png" width="640" /></a></div>
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<span style="font-family: Verdana, sans-serif;">Artificial
Intelligence is the broad umbrella term for attempting to make computers think
the way humans think, be able to simulate the kinds of things that humans do
and ultimately to solve problems in a better and faster way than we
do. Then, machine learning refers to any type of computer program that can
“learn” by itself without having to be explicitly programmed by a
human. Deep learning is one of many approaches to machine learning. Other
approaches include decision tree learning, inductive logic programming,
clustering, reinforcement learning, and Bayesian networks. Deep learning was
inspired by the structure and function of the brain, namely the interconnecting
of many neurons.</span><o:p></o:p></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">Some of the discussions on deep learning are intriguing. Does it lead to machines taking over jobs?</span></div>
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<span style="font-family: Verdana, sans-serif;">Machines are getting smarter because we’re getting better at
building them. And we’re getting better at it, in part, because we are smarter
about the ways in which our own brains function.</span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
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<span style="font-family: Verdana, sans-serif;">Despite the massive potential of AI systems, they are still
far from solving many kinds of tasks that people are good at, like tasks
involving hand-eye coordination or manual dexterity; most skilled trades,
crafts and artisan- ship remain well beyond the capabilities of AI systems. The
same is true for tasks that are not well-defined, and that require creativity,
innovation, inventiveness, compassion or empathy. However, repetitive tasks
involving mental labor stand to be automated, much as repetitive tasks involving
manual labor have been for generations.<o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">Let me give you an example your calculator is smarter than
you are in arithmetic already; your GPS is smarter than you are in spatial
navigation; Google, Bing, are smarter than you are in long-term
memory. And we're going to take, again, these kinds of different types of
thinking and we'll put them into, like, a car. The reason why we want
to put them in a car so the car drives, is because it's not driving like a
human. It's not thinking like us. That's the whole feature of
it. It's not being distracted, it's not worrying about whether it
left the stove on, or whether it should have majored in finance. It's
just driving.<o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">What are the
domains that you see would see faster adoption & benefits of these
techniques? <o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">In healthcare, deep learning is expected to extend its roots
into medical imaging, translational bioinformatics, public health policy
development using inputs from EHRs and beyond. There is rapid improvements in
computational power, fast data storage and parallelization have contributed to
the rapid uptake of deep learning in addition to its predictive power and
ability to generate automatically optimized high-level features and semantic
interpretation from the input data.<o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">Seems like the
ASIC design flow/process can be equally benefited from these techniques. Your
views on it?<o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;">Deep Learning in its elements is an optimization problem.
Its application in any work flow or design process where there is scope for
optimization carries enormous benefits. With respect to the design, fab and
bring up of ICs, deep learning helps with inspection of defects, determination
of voltage and current parameters, and so. In fact, at NVIDIA we carry out
rigorous scientific research in these areas. I believe as we unlock more
methods of unsupervised learning, we’ll discover and explore many more
possibilities of efficient design where we don’t entirely depend of large
volumes of labelled data which hard to get in such a complex practice. <o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">What are the
error rates in execution we can expect with deep learning? Can we rely on
machines for life critical applications?<o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
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<span style="font-family: Verdana, sans-serif;">Deep learning will certainly out-perform us in few specific
tasks with very low error rates. For example, classification of images is task
where models can be far accurate than mortals. Consider the case of language
translation, today machines are capable of such efficient and economic
multi-lingual translation that it wouldn’t just be possible for a person.
[Recently MSFT’s speech recognition systems achieved a word error rate of
5.1%on par with humans] While we look into health care where life critical
decisions are made, deep learning can be used to improve accuracy, speed and
scale in solving problems like screening, tumor segmentation, etc. and not
necessarily declaring a person alive or otherwise! <o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
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<span style="font-family: Verdana, sans-serif;">In all the instance we just saw, state-of-art capabilities
are developed in very specific and highly verticalized applications. Machine
are smarter than us in these applications but nowhere close to our general intelligence
in piecing these inputs together to make logical conclusions. From a pure
systems and software standpoint, we will need guard rails, i.e. fail-safe
heuristics that backup a model when it operates outside the boundaries to keep
the fault tolerance at bay. <o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">This is the 4<sup>th</sup>
edition of DVCon in India. What are your expectations from the conference? <o:p></o:p></span></div>
<br />
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<span style="font-family: Verdana, sans-serif;">While the 20th century is marked by the rise and dominance
of the United States, the next 100 years are being dubbed the </span><b style="font-family: Verdana, sans-serif;">Asian Century</b><span style="font-family: Verdana, sans-serif;"> by</span><span style="font-family: Verdana, sans-serif;"> many prognosticators. No country is driving this tectonic shift more than India
with its tech talent. NVIDIA is a world leader in artificial intelligence
technologies and is doing significant work to train the next generation of deep
learning practitioners. Earlier this year we announced our plans to train
100,000 developers in FY18 in deep-learning skills. We are working across
academia and the startup community to conduct trainings in deep learning. I’m
keen to understand the enthusiasm of the attendees in these areas and how
NVIDIA can provide a bigger platform and bring the AI researchers and
scientists community together. </span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;">Thank you Vishal!</span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
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<span style="font-family: Verdana, sans-serif;"><a href="https://dvcon-india.org/registration/rates">Join us</a> on <a href="https://dvcon-india.org/agenda/2017-9-14">Day 1 (Sep 14)</a> of <span style="color: #f1c232;">DVCon India 2017</span> at Leela Palace, Bangalore to attend this keynote and other exciting topics!</span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
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<span style="font-family: Verdana, sans-serif; font-size: xx-small;"><i>Disclaimer: "The postings on this blog are my own and not necessarily reflect the view of Aricent"</i></span></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com1tag:blogger.com,1999:blog-9157206405178843096.post-41625377983216109072017-08-27T15:56:00.001+05:302017-08-29T22:13:45.497+05:30Quick chat with Ravi Subramanian : Keynote speaker DVCon India 2017<div dir="ltr" style="text-align: left;" trbidi="on">
<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: left; margin-right: 1em; text-align: left;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_VlsmA5I3QM_G57-y-q_cLlMrfwcNJUnm20LoRMvE06mNBAkPvToKtQjxukOJynGDciBgZdgQ9blx9N4nhyphenhyphenpXDVOr_6ck_2fNeol3IX7TnB5_VXV0q5u0ishe62pCYYZ9YzwmbfQqFpE/s1600/86+-+R.+Subramanian.jpg" imageanchor="1" style="clear: left; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" data-original-height="1200" data-original-width="857" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_VlsmA5I3QM_G57-y-q_cLlMrfwcNJUnm20LoRMvE06mNBAkPvToKtQjxukOJynGDciBgZdgQ9blx9N4nhyphenhyphenpXDVOr_6ck_2fNeol3IX7TnB5_VXV0q5u0ishe62pCYYZ9YzwmbfQqFpE/s200/86+-+R.+Subramanian.jpg" width="142" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i>Dr. Ravi Subramanian</i></td></tr>
</tbody></table>
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<span style="font-family: "verdana" , sans-serif;">For many decades, the semiconductor industry followed <a href="http://whatisverification.blogspot.in/2015/04/moores-law-journey-of-50-years.html">Moore’s law</a>, transforming what we called as a discrete chip carrying a function on
silicon into a small IP inside the SoC on silicon today. As we
continue to debate beyond Moore, more than Moore or stagnation of this law and
step in the world of IoT, we realize that the system is no more only a single SoC, but
instead, it is a conglomeration of multiple tiny & large systems working in
tandem producing interesting use cases & enhancing user experience. But are
we as the verification engineering workforce <a href="http://whatisverification.blogspot.in/2015/10/the-magical-chariot-in-verification.html">ready</a> with the required skills along
with the right arsenal of tools and efficient workhorses to ride through this
new challenge?</span></div>
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<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Dr. Ravi Subramanian, Vice president and General manager of
<a href="https://www.mentor.com/">Mentor’s</a> IC Verification Solutions Division shares a holistic view on this
subject in his opening <a href="https://dvcon-india.org/content/event-details?id=241--86">keynote</a> on Day 2 at <a href="https://dvcon-india.org/">DVCon India 2017</a>. The talk titled <span style="color: #f1c232;">Innovations
in Computing, Networking, and Communications: Driving the Next Big Wave in
Verification</span>, dives into convergence of different technologies and its impact
on verification. A quick chat with Ravi, revealed the excitement that we all
can look forward to in his talk as well as the future that lies ahead for all
of us. Read on!!!</span></div>
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<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">Ravi your
keynote focusses on drivers to the next big wave in verification. Tell us more
about it?</span></span></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;"><br /></span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Yes, my talk will focus on the amazing innovations our industry
is developing with respect to computing, networking, and communications. These
include the changing nature of computing, the dramatic changes in networking
and storage, and the disruptive effect of new broadband communications. Yet,
the next big wave in design is actually the convergence of these technologies,
which is driving today’s internet-of-things and autonomous systems revolution.
A common theme across these emerging systems is the need for low power,
security, and safety—whether you are talking about devices on the edge or
high-availability systems in the cloud. These new challenges have opened
innovation opportunities for us to rethink the way we approach verification<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">IoT is driving
the convergence of different technologies. How would it affect the way we
verify the systems today? <o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: "verdana" , sans-serif;">To answer your question, I first want to step back in time
to provide a framework for today’s challenges. In the 1990’s the concept of <i>separation
of concerns</i> was introduced into engineering. Essentially, the idea is that
verification would become more productive if we focused on verifying orthogonal
concerns or requirements of the design separately versus trying to verify
multiple concerns combined. For example, during this period of time, we learned
that it is more efficient to verify functional concerns and physical concerns
in separate simulation runs. This approach to verification worked well up to
about 10 years ago. The emergence of mobile devices introduced new low-power
requirements that made it difficult to separate concerns. For example, today we
see that physical concerns (such as low power management) now can directly
affect functional behavior of a device. Hence, these concerns need to be
verified together. Bringing together physical, electrical, and functional has
become mandatory.<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">The key point is that convergence of computing, networking,
and communication, which is driving IoT, has introduced new layers of
verification requirements that did not exist years ago, and the interaction of
these requirements has had a profound effect on the way we must verify systems
today.</span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">What are the
solutions that the EDA industry is driving to enable this next big wave in
verification?<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">One contributing factor to growing verification complexity
is the emergence of new layers of verification requirements, as I previously
mentioned. For example, beyond the traditional functional domain, we have added
clock domains, power domains, mixed-signal domains, security domains, safety
requirements, software, and then obviously, overall performance requirements.
Hence, we see the next big wave in verification on multiple fronts:<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: "verdana" , sans-serif;">Continuing introductions of focused solutions optimized for
specific verification concerns. Examples of these focused solutions include:
formal apps focused on verifying security features within a design or
power apps used to provide complete RTL power exploration and accurate
gate-level power analysis within emulation.<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Emerging system-level analysis solutions, which provide new
metrics and insight into the fully integrated SoC. This becomes essential for
system-level performance analysis. The IoT SoC, for example, is a different
beast than today’s state-of-the art networking SoC.<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Greater convergence across multiple verification engines
(e.g., simulation, emulation, and FPGA prototyping), which will improve
productivity. The new Accellera Portable Stimulus standard will help facilitate
this convergence and foster the introduction of new verification solutions.<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Q4: Do you see
domain specific solutions like automotive or machine learning etc. getting
enabled for verification?<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Yes, in fact there are multiple opportunities to leverage
big data analytics to solve many system-level analysis problems. Machine
learning is only one approach used today for big data analytics; however, there
are others. Now, concerning domain-specific solutions in the automotive space,
formal technology is being leveraged to improve productivity related to safety
fault analysis. <o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Do you expect
all workhorses (Simulation, Emulation & Formal) playing a critical role in
verifying these new converged system level designs?<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Obviously, this depends on the design. A project developing sensors
for an IoT edge solution has different verification requirements than a project
developing an automotive SoC containing multiple CPU and GPU cores, a coherent
fabric, and multiple complex interfaces. Nonetheless, with increased design
integration, multiple verification engines are required today that address the
growing volume of verification requirements.<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">This is the 4<sup>th</sup>
edition of DVCon in India. What are your expectations from the conference? <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">DVCon, in general, is recognized as the premier conference
on the application of languages, tools, methodologies and standards for the
design and verification of electronic systems and integrated circuits. And
DVCon India is no exception, which has continued to grow in both attendance and
exhibitor participation. I expect DVCon 2017 will continue to deliver
high-quality technical content and provide valuable networking opportunities
for its attendees. It is the premier venue to share state-of-the-art
developments and connect the creative minds working on these developments.<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">Thank you Ravi!</span><o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><a href="https://dvcon-india.org/registration/rates">Join us</a> on <a href="https://dvcon-india.org/agenda/2017-9-15">Day 2 (Sep 15)</a> of <span style="color: #f1c232;">DVCon India 2017</span> at Leela
Palace, Bangalore to attend this keynote and other exciting topics.<o:p></o:p></span></div>
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</div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<o:p><span style="font-family: "verdana" , sans-serif;"><br /></span></o:p></div>
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<o:p></o:p></div>
<div class="MsoNormal">
<span style="font-family: "verdana" , sans-serif; font-size: xx-small;"><i>Disclaimer: “The postings on this blog are my own and not necessarily
reflect the views of Aricent”</i></span><o:p></o:p></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com3tag:blogger.com,1999:blog-9157206405178843096.post-22155244063543540122017-08-20T22:26:00.000+05:302017-08-20T22:26:52.705+05:30Quick chat with Apurva Kalia : Keynote speaker DVCon India 2017<div dir="ltr" style="text-align: left;" trbidi="on">
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: right; margin-left: 1em; text-align: right;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgesibqPgxJrHJ4kE8Chnk2L0LIi6LLHeDRtFZkg_cc3Tlv3RJTe1heH5gXdDPslJd8dgX5FjAaml5KEoF9H0w2tAywwnpbfCH0stUn81N5_OV8o1V2qMq8K8cnihrz19JuFNj6tdwu7ps/s1600/84+-+Apurva+Kalia.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" data-original-height="567" data-original-width="441" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgesibqPgxJrHJ4kE8Chnk2L0LIi6LLHeDRtFZkg_cc3Tlv3RJTe1heH5gXdDPslJd8dgX5FjAaml5KEoF9H0w2tAywwnpbfCH0stUn81N5_OV8o1V2qMq8K8cnihrz19JuFNj6tdwu7ps/s200/84+-+Apurva+Kalia.jpg" width="155" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="font-family: Verdana, sans-serif; font-size: x-small;"><i>Apurva Kalia</i></span></td></tr>
</tbody></table>
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<span style="font-family: Verdana, sans-serif;">The advancements in semiconductor industry starting picking
up with the rise in performance of processors driving the computer industry. Next, the mobile segment opened floodgates when the PC market stagnated & then
low power with smaller dimensions on top of performance drove the innovation in
silicon implementation. The industry today is at cross roads once again
awaiting the next big thing. <span style="color: #f1c232;">Automotive</span> is one of the key areas to get the ball
rolling yet again. But then, each domain has its characteristics that needs to
be aligned to! <o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Apurva Kalia, Vice President of R&D focusing on
Automotive solutions at <a href="http://www.cadence.com/">Cadence</a> picks on an interesting topic for his <a href="https://dvcon-india.org/content/event-details?id=241--84">DV track keynote</a>
on <a href="https://dvcon-india.org/agenda/2017-9-14">Day 1</a> at <a href="https://dvcon-india.org/">DVCon India 2017</a>. With the auto industry shifting gears into
autonomous cars, the question worth asking is – <span style="color: #f1c232;">Would you send your child to
school in an autonomous car?</span> Yes, that’s the theme of Apurva’s keynote and here’s
a sneak peek on this topic. <o:p></o:p></span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Apurva your keynote focusses on ‘autonomous cars’ – the
talk of the town these days. Tell us more about it?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Well, there is major inflection point coming up in automotive
electronics. We all know that Moore’s Law driven advances in cost per
transistor and capacity have been holding up for many years. Complex chips are
now possible within a cost factor that was not possible earlier. Moreover
advances in algorithms, especially Machine Learning, now enables much more
complex processing, especially vision based processing, to be done in real
time. Both these trends coming together with advances in sensor technology has
enabled systems to be created which can detect their environment quite
accurately and in real time. This is the basis of autonomous driving. Also, as
we know, every few years the semiconductor industry is looking for the next big
trend which will drive the fab capacity. The above factors are pushing
autonomous driving to be the talk of the town.<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Security & Safety are emerging areas resulting from
this topic. How does this change the way we verify our designs?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">As I described above, with autonomous driving really taking
off, these systems are becoming mission critical for the automobile. This means
that the system needs to be safe and secure. It is inconceivable for a car to
stop working at 80 kmph on a highway! Also, with the car needed to be connected
to other cars and even to infrastructure and internet, this opens the system to
attacks and makes it vulnerable. Therefore, these systems needs to make safe
and secure to ensure safety and security of the automobile.<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">What are the solutions that the EDA industry is driving
to enable ISO 26262 requirements from process & product perspective?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">ISO26262 is the main standard that defines the safety
requirements for automobiles. It is a very comprehensive standard which places
requirements on all automotive systems. In fact edition 2 of the standard –
coming out in Jan 2018 – will focus specially on semiconductors. Given the
excitement around automotive electronics and autonomous systems, EDA industry
needs to retool rapidly to address this need. Ensuring safety in these designs
requires additional design and verification flows, methodologies and tool
changes. The EDA industry needs to step up to define and create these flows,
methodologies and tools required.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">What are your views on the couple of accidents that
happened in the US with autonomous cars? What could have been done better?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">We are at early stages of this technology. Unfortunately as
with any new technology, technology will take time to stabilize. In the
meantime, during this stabilization time, unfortunate things like these
accidents could happen. Organizations and individuals who are early adopters of
these technologies take these risks, but they also contribute in a big way for
advancement of these technologies. However, with the proper use of tools,
implementation of standards, and focus on new solutions, we can avoid these
kind of accidents.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">How do you observe the adoption of autonomous cars
across the globe & in India?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Autonomous cars are here to stay. They are solving real
problems in real environments. We already have examples of autonomous cars on
real roads – driving very safely. In fact, there are statistics which show that
autonomous cars will actually cut down on accidents and fatalities – the most
of which are caused by human error. Last year, I saw an engineering college in
Delhi demonstrate an autonomous vehicle in Govindpuri – one of the most
congested areas of Delhi. So this technology is real and works. I think it is
just a matter of a few years when we will see this mainstream.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Do you see all workhorses (Simulation, Emulation &
Formal) playing a critical role in realizing Auto grade designs?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Yes – all current EDA technologies – not just verification
technologies, but even implementation technologies – need to be upgraded to support
safety and security design and verification. All engines will need enhancements
and special features to support these new requirements and flows.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">This is the 4<sup>th</sup> edition of DVCon in India.
What are your expectations from the conference? <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">I have seen DVCon India grow from humble beginnings to an
excellent conference today. I think this conference provides a very good
platform to share and discuss new trends in design and verification. I look
forward to stimulating conversations on new flows and technologies. This
conference attracts many design companies and all EDA vendors in India – what
better assemblage of the right people for these discussions. <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;">Thank you Apurva!<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><a href="https://dvcon-india.org/registration/rates">Join us</a> on Day 1 (Sep 14) of <span style="color: #f1c232;"><b>DVCon India 2017</b></span> at Leela
Palace, Bangalore to attend this keynote and other exciting topics.<o:p></o:p></span></div>
<br />
<div class="MsoNormal" style="text-align: justify;">
<i style="font-family: Verdana, sans-serif; font-size: x-small;"><br /></i></div>
<div class="MsoNormal" style="text-align: justify;">
<i style="font-family: Verdana, sans-serif; font-size: x-small;">Disclaimer: “The postings on this blog are my own and not
necessarily reflect the views of Aricent”</i></div>
<div class="MsoNormal" style="text-align: justify;">
<o:p></o:p></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com1tag:blogger.com,1999:blog-9157206405178843096.post-19233197093471940402017-03-27T12:03:00.000+05:302017-03-29T18:49:54.420+05:30Ni Hao China? says DVCon<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;">Miniaturization
of devices is marching into the range where the acceleration may not be
contained in one dimension anymore. This is leading to growth in 2D & 3D
for packing more functions on a given silicon area. One of the key factors that has enabled this race so far is also the globalization of workforce. Whether the reasons were tapping the
talent world-wide or ensuring the work continues round the clock or reduce cost
of development. With the tech world turning into a global village, there was a need
felt to ensure different age groups, different cultures & different working
styles, talk a common language. This has been the prime motive of <a href="http://www.accellera.org/">Accellera</a> working
groups getting together from across the world to define standards and
methodologies and providing a common ground for everyone to contribute. <span style="font-family: Verdana, sans-serif;">While rolling
out standards is a key outcome of this consortium, encouraging the adoption
& ensuring correct application of these standards is equally important. This
is one of the prime reasons that the flagship conference </span><a href="https://dvcon.org/"><span style="font-family: Verdana, sans-serif;">DVCon</span></a><span style="font-family: Verdana, sans-serif;"> was extended
beyond geographies (</span><a href="http://whatisverification.blogspot.in/2014/07/dvcon-goes-global.html"><span style="font-family: Verdana, sans-serif;">DVCon goes GLOBAL!</span></a><span style="font-family: Verdana, sans-serif;">) a few years back when </span><a href="https://dvcon-india.org/"><span style="font-family: Verdana, sans-serif;">India</span></a><span style="font-family: Verdana, sans-serif;"> &
</span><a href="https://dvcon-europe.org/"><span style="font-family: Verdana, sans-serif;">Europe</span></a><span style="font-family: Verdana, sans-serif;"> embraced it with an overwhelming response. This year the 29th <span style="font-size: x-small;">
edition of DVCon US witnessed 1000+ participants over a 4-day conference continuing the momentum year after year. However, this caravan would see another
stopover before it reaches India in September this year. <span style="color: orange;"><strong>YES!!!</strong></span> DVCon would be debuting
in the Mandarin land this year - <a href="https://dvcon-china.org/">DVCon China 2017</a>!!!</span></span></span></span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj1iE7ODFfj0urgsnmKfgfcK-uZuLMy4W8KgUIHjb1MFxpVSQQuSIZqA529cUxrKqBJdHUglygeYYE1hqzvVInXF2_jO_n5qR4uO21sg9bAQg9PZFf3A8tWvQWy8IcERoCRyHXleJWzhEY/s1600/2016_DVConCN_HomepageTagline.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-left: 1em;"><img border="0" height="160" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj1iE7ODFfj0urgsnmKfgfcK-uZuLMy4W8KgUIHjb1MFxpVSQQuSIZqA529cUxrKqBJdHUglygeYYE1hqzvVInXF2_jO_n5qR4uO21sg9bAQg9PZFf3A8tWvQWy8IcERoCRyHXleJWzhEY/s640/2016_DVConCN_HomepageTagline.png" width="640" /></a></div>
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<span lang="EN" style="mso-ansi-language: EN;"></span><br />
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<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;">If you have
any doubts on why China? Let’s review a few interesting pointers from the
latest report by PWC titled China’s <a href="http://www.pwc.com/gx/en/technology/chinas-impact-on-semiconductor-industry/assets/china-impact-of-the-semiconductor-industry-2016-update.pdf">impact on the semiconductor industry : 2016update</a>. </span></span></div>
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<span lang="EN" style="mso-ansi-language: EN;"></span><br />
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<ul style="text-align: left;">
<li><div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"></span><span style="font-family: "verdana" , sans-serif;">China’s semiconductor consumption growth continued to far exceed worldwide semiconductor market growth for the 5th consecutive year in 2015 reaching a new record of <strong>58.5%</strong> of the global market. China’s semiconductor industry has grown at an equal or greater rate than its semiconductor market consumption for <strong>eight</strong> of the past ten years. In 2015, China’s semiconductor industry grew by <strong>15.5%</strong> to a record <strong>US$89.3bn</strong>.</span></div>
</li>
<li><div style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">China’s IC industry grew by <strong>17.1%</strong> in 2015 despite a decline in the global IC market. Since 2010 China’s IC industry revenues have more than <strong>doubled</strong>, growing <strong>170%</strong>. Starting from a very small US$2.2bn base in 2000, China’s IC industry has grown much faster than the worldwide IC market for every subsequent year except 2010 with revenue touching 2015 to <strong>US$57.5bn</strong>. </span></div>
</li>
<li><div style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Integrated circuit (IC) design continues to be the fastest growing segment of China’s semiconductor industry. During the ten years from 2005 through 2015 China’s IC design (fabless) industry has grown at a <strong>30.1%</strong> compound annual growth rate (CAGR) from <strong>US$1.52bn</strong> to just over <strong>US$21bn</strong> in 2015.</span></div>
</li>
<li><div style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">The China Center of Information Industry Development (CCID) reports that the number of China’s IC design enterprises increased from 681 in 2014 to <strong>715</strong> by the end of 2015 with the total number of employees in China’s IC design totaling to about <strong>155,000</strong>. </span></div>
</li>
</ul>
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<span style="font-family: "verdana" , sans-serif;">T</span><span style="font-family: "verdana" , sans-serif;">hese pointers clearly confirm that the semiconductor
industry is growing in China at an unparalleled speed and hosting a conference
to bring in the stakeholders together would further stimulate the development
process. Clearly a thoughtful decision by <a href="http://www.accellera.org/">Accellera</a>!</span></div>
<div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;"><br /></span></span></div>
<div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;">Coming back to the details of the
event, the 1st edition of the <a href="https://dvcon-china.org/">Design and Verification Conference and ExhibitionChina</a> is planned for <strong><span style="color: orange;">19, April 2017</span></strong> at the <strong><span style="color: orange;">Parkyard Hotel, Shanghai</span></strong>. DVCon
China provides an excellent platform to bring together the global semiconductor
industry in general & the China semiconductor industry in particular, along
with academia and international standards development organizations. The <a href="https://dvcon-china.org/agenda">1 fullday event</a> is completely packed with an assortment of keynotes from eminent
speakers, tutorials from the gurus, papers & posters from practitioners and
avenues for networking, learning opportunities, and exciting exhibits with
different offerings. Along with experts from China there is an active
participation from universities like Tsinghua and Fudan as part of the DVCon
China steering and program committees. The day starts with keynote from <strong>Dr.
Wally Rhines</strong> - CEO Mentor Graphics on the topic <a href="https://dvcon-china.org/content/event-details?id=224-302">Design Verification:Challenging Yesterday, Today and Tomorrow</a> while the event concludes with
another interesting talk on <a href="https://dvcon-china.org/content/event-details?id=224-301">What's Next in Verification</a> from <strong>Yong Fu</strong> – Group Director, Synopsys. </span></span></div>
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<span lang="EN" style="mso-ansi-language: EN;"></span><br />
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<span lang="EN" style="mso-ansi-language: EN;"></span><span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;">Leaders from the local industry
with extended support from experts across the globe have put together a
fantastic program for you to actively participate in person and be part of this
enriching experience. </span></span></div>
<div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;"></span></span><br />
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<div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana" , sans-serif;">Reiterating the words of Benjamin Franklin that truly exhibit the
spirits of DVCon–</span></span></div>
<div style="text-align: justify;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana";"><br /></span></span></div>
<div style="text-align: center;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="color: #f1c232; font-family: "verdana";"><em>Tell me and I forget.</em></span></span></div>
<div style="text-align: center;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="color: #f1c232; font-family: "verdana";"><em>Teach me and I remember.</em></span></span></div>
<div style="text-align: center;">
<span lang="EN" style="mso-ansi-language: EN;"><span style="color: #f1c232; font-family: "verdana";"><em>Involve me and I learn.</em></span></span></div>
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<span lang="EN" style="mso-ansi-language: EN;"><span style="font-family: "verdana";"><br /></span></span></div>
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<span style="font-family: "verdana" , sans-serif;">
</span><br />
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<span style="font-family: "verdana" , sans-serif;"><span style="color: orange;"> Get involved NOW!!!</span> </span><span style="color: orange; font-family: "verdana";"><span lang="EN" style="mso-ansi-language: EN;">Registrations open with early bird discounts - <a href="https://dvcon-china.org/registration/rates">here</a></span></span></div>
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<div style="text-align: left;">
<span style="font-size: x-small;"><em>Disclaimer: "The postings on this are my own and not necessarily reflect the views of Aricent".</em></span></div>
</div>
</div>
</div>
</div>
</div>
</div>
</div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com2tag:blogger.com,1999:blog-9157206405178843096.post-24036148164044723952016-09-09T10:35:00.000+05:302016-09-09T10:39:11.199+05:30Quick chat with Alok Jain : Keynote speaker, DVCon India 2016<div dir="ltr" style="text-align: left;" trbidi="on">
<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: right; margin-left: 1em; text-align: right;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiH8jo0puhZipBmhi2pmEwLoyv0IeaH_vXXP0Y7ZnMPcl1xm4wqRX2cvqdGgWFTEXYke5p0qGvpJCE_FGAjix4Jypth6Y6NpIEwK4WzpgKZKYCu7M-abDegr6h8Yy-w1iI-KBc71pz0r5Q/s1600/Alok.jpg" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiH8jo0puhZipBmhi2pmEwLoyv0IeaH_vXXP0Y7ZnMPcl1xm4wqRX2cvqdGgWFTEXYke5p0qGvpJCE_FGAjix4Jypth6Y6NpIEwK4WzpgKZKYCu7M-abDegr6h8Yy-w1iI-KBc71pz0r5Q/s200/Alok.jpg" width="200" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i>Alok Jain</i></td></tr>
</tbody></table>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">All of us have heard the story of a woodcutter and the
importance of the quote <span style="color: #f1c232;">“Sharpen your axe”</span>. It applies well to everything we do
including verification. Two decades back, the focus of a verification engineer
was predominantly on “<span style="color: #f1c232;">What to Verify</span>”. As complexity grew “<span style="color: #f1c232;">How to Verify</span>”
became equally important. To enable this, EDA teams rolled out multiple
technologies & methodologies. As we try to assimilate & integrate these
flows amidst first time silicon & cost pressure, it is important for us to
sharpen our axe through continuous learning, applying the right tool for
the right job and applying it effectively. <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Alok Jain, Senior Group Director in the Advanced
Verification Division at <a href="https://www.cadence.com/">Cadence</a> would be discussing on similar lines as part
of his <a href="https://dvcon-india.org/content/event-details?id=205-53">DV track keynote</a> on Day 1 at <span style="color: #f1c232;"><b>DVCon India 2016</b></span>. With 20+ years of
industry experience, Alok leads the Advanced Verification Division at Cadence
India. Having associated with different technologies around verification in the
past 2 decades, Alok candidly shared his views on the challenges beyond
complexity that verification teams need to focus on. Here is a curtain raiser
for his talk <span style="color: #f1c232;">"Verification of complex SoCs" </span>–<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Alok your keynote topic focuses on challenges in
verification beyond the complexity resulting from Moore’s law. Tell us more
about it?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">The keynote is going to focus on challenges and potential
solution for verification of complex SoCs. Verifying a complex SoC consisting
of tens of embedded cores and hundreds of IPs is a major challenge in the
industry today. One of the big challenges is performance and capacity. Given
the size and complexity of modern SoCs, tests can run for 18-24 hours or even
more. One has to figure out how to get the best verification throughput.
Another challenge is generation of test benches and tests. The test benches have
to be developed in a way which can achieve good performance in both simulation
and hardware acceleration. Tests have to be created that stress the SoC under
the application use cases, low power scenarios, and multi-core coherency
scenarios. The tests have to be re-usable across pre-silicon and post-silicon
verification and validation platforms. Yet another challenge is coverage. One
has to measure verification coverage across formal, simulation, and
acceleration platforms at the SoC level to know when you are done. The final
challenge is how to effectively debug across RTL, test bench, and embedded
software on multiple verification platforms.<o:p></o:p></span></div>
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<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">In the last decade, advancements in verification was focused
primarily on unifying HVL(s) & methodologies. What changes do you foresee
in verification flows ‘Beyond UVM’?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">UVM is very well suited for IP, Sub-system and some specific
aspects of SoC verification. However, UVM is not the best approach for general
SoC verification. UVM is essentially developed for “bottom-up” verification
where the focus is on trying to exhaustively verify IP/sub-systems. SoCs
require a more “top-down” verification where the focus is on stressing the SoC
under important application use cases. There is a need to reuse SoC content
across simulation, emulation, FPGA and post-silicon. UVM is optimized for
simulation and is too slow and heavy for high speed platforms. Finally, there
is a need to drive software stimulus on CPUs in coordination with hardware
interfaces. It is difficult in UVM to drive and control software and hardware
interfaces. All this is asking us to explore options beyond UVM. The keynote
will cover some more insights into options beyond UVM.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232;"><span style="font-family: "verdana" , sans-serif;">The rise of IoT is stretching the design demands to far
ends i.e. server class vs edge node devices. </span><span style="font-family: "verdana" , sans-serif;">How do you see verification flows catering to these demands?</span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Several of the requirements for IoT verification are similar
to the ones for complex SoCs. But then there are some unique additional
requirements from the IoT world. The first is simply the cost of verification.
For complex SoCs, the cost of verification has been steadily rising. For IoT
applications, one has to consider alternative methods and flows that can reduce
the cost. One option is to use some form of a correct by construction approach
where the design is specifically done in a way to enable a simpler form of
verification. Another approach is to put much more emphasis on reuse. This
includes horizontal reuse which is portability across multiple platforms and
vertical reuse which is reuse from IP to sub-system to SoC. Another requirement
is verification throughput for design with considerably more analog, mixed signal
and low power content. Finally, one has to devise verification techniques and
flows that can cater to the security and safety requirements of modern IoT
applications. <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Formal took a while to become mainstream. The rise of Apps
in Formal seems to have accelerated this adoption. What’s your view on this? <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Yes, I do agree that Apps has considerably accelerated the
pace of adoption of formal. Traditionally, formal tools have been developed and
used by formal PhDs and experts. The main charter and motivation of these
experts was to solve the coolest and hardest problems in formal verification.
It was only after some time that both sides (developers and users) started
realizing that formal can be used in a much more practical and usable way by
engineers to solve specific problems. This lead to the development of various
formal apps which greatly enabled the mainstream usage of formal.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">This is the 3rd edition of DVCon India. What are your
expectations from the conference?<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">I am expecting to attend keynotes, technical papers and
panel discussions that give me an understanding of some the latest work in the
domain of design and verification of IPs, sub-systems and SoCs. In addition, I
am looking forward to the opportunity to network with some of my peers from the
industry and academia.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Thank you Alok! <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<br />
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">Come <a href="https://dvcon-india.org/registration/rates">join us</a> in this exciting journey to <span style="color: #f1c232;">contribute,
collaborate, connect & celebrate</span> @ <a href="http://www.dvcon-india.org/">DVCon India 2016</a>!</span><o:p></o:p></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<i style="font-family: verdana, sans-serif;"><span style="font-size: x-small;">Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”</span></i></div>
</div>
<div class="blogger-post-footer"><a href="https://twitter.com/share" class="twitter-share-button" data-via="gjalan">Tweet</a>
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<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: left; margin-right: 1em; text-align: left;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgT3jCI79N10MADjejJTtvs0yW8-Me-cOq1BpHJYN-2War9LZHXBGJorrWbx4z5R11dfr1-_n9nQdLY43Q7CBaEWQjxceDWDhqPY7CdMCnjuoAOyM4vWddodSJp0tGLFBp5BNORIvF70WU/s1600/Sushil.png" imageanchor="1" style="clear: left; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgT3jCI79N10MADjejJTtvs0yW8-Me-cOq1BpHJYN-2War9LZHXBGJorrWbx4z5R11dfr1-_n9nQdLY43Q7CBaEWQjxceDWDhqPY7CdMCnjuoAOyM4vWddodSJp0tGLFBp5BNORIvF70WU/s1600/Sushil.png" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i>Sushil Gupta</i></td></tr>
</tbody></table>
<div class="MsoNormal" style="margin-bottom: 0.0001pt; text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">A very famous urdu <a href="https://rekhta.org/couplets/main-akelaa-hii-chalaa-thaa-jaanib-e-manzil-magar-majrooh-sultanpuri-couplets">verse</a> that translates </span><span style="font-family: "verdana" , sans-serif;"> translates to <span style="color: #f1c232;">“When I
started I was alone, slowly others joined and a caravan formed”</span> truly
describes the plethora of challenges in SoC verification that continues to
abound as the design complexity marches north. It started with growing logic on
the silicon and moved to performance before power took over. While we still
juggle up to handle the PPA implications, time to market pressure with cost
effective secure customized solutions further add enough spice to the problem.</span></div>
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<span style="font-family: "verdana" , sans-serif;">Sushil Gupta, Group Director in the Verification group at
<a href="http://www.synopsys.com/home.aspx">Synopsys</a> covers these problems & potential solutions in his <a href="https://dvcon-india.org/content/event-details?id=205-70">keynote</a> titled <span style="color: #f1c232;">“Today’s
SoC Verification Challenges: Mobile and Beyond” </span>on <a href="https://dvcon-india.org/agenda/2016-9-16">Day 2 </a>of <b><span style="color: #f1c232;">DVCon India 2016</span></b>. Sushil
joined Synopsys in 2015 as part of acquisition of Atrenta. He has 30 years of
industry experience which spans various roles in engineering management and
leadership in EDA and VLSI Design companies. Here is a quick excerpt of the
conversation with Sushil around this topic –<o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Sushil your keynote topic focuses on challenges in
verification associated with the next generation of SoCs. Tell us more about
it?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">We have seen the chip design industry shift its focus from
computers and networking into System on Chips (SoC) for mobility – smartphones,
tablets, and other consumer devices. The next wave of SoCs go beyond mobility
into IoT, automotive, robotics, etc. These SoCs integrate hundreds of functions
into a single chip and a complete software stack with drivers, operating
system, etc.. The result is 10X increase in verification complexity in
continually shrinking market windows. My talk focuses on these challenges and
how verification solutions must scale to address them effectively. <o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">Reuse of IP/Subsystems is the key trend with SoCs
today. Do you think that reuse from third party add to challenges in
verification? If yes, how?</span></span></div>
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<span style="font-family: "verdana" , sans-serif;">IP/sub-system reuse (both third party and in-house) helps
accelerate the integration of multiple functions into a single chip. However,
these IP/sub-systems can come from multiple sources with heterogeneous design
and verification flows. The resulting SoCs are extremely complex with
millions of lines of RTL and testbench, protocols, assertions, clock and
power domains, and billions of cycles of OS boot. <o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Do you think progress in verification methodologies
& flows have reached to a point where consolidation is key to allow
verification engineer use the best of each? Any specific trends that you would
like to highlight on this?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Integrated verification platforms are key to verification
convergence. Verification now extends beyond functional verification into low
power verification, debug automation, static and formal verification,
early software bring-up and emerging challenges with safety, security and
privacy. This requires not only best-in-class verification tools and engines,
but also native integrations between the tools to enable seamless transitions
and faster convergence. <o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Sushil you have had a significant stint with formal at
Atrenta. What are your thoughts on adoption of Formal coming to mainstream? How
does the trend looks moving forward?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Formal is fast becoming mainstream because it can catch bugs
that are otherwise very difficult to detect. Advancements in performance, debug
and capacity of formal verification tools has enabled formal to become an
integral part of a comprehensive SoC verification flow. The emergence of formal
‘Apps’ for clock and reset domains, low power, connectivity, sequential
equivalence, coverage exclusions, etc. has enabled a broad range of design and
verification engineers to benefit from formal verification without the need to
be a formal “expert”. <o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">This is the 3rd edition of DVCon India. What are your
expectations from the conference?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Speaking from my own experience having started my career
with TI India in 1986, India has a very rich design and verification expertise.
I hope to learn about the latest challenges and innovations in verification and
look forward to working with our customers and partners on new breakthroughs. <o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">Thank you Sushil! </span><o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;"><a href="https://dvcon-india.org/registration/rates">Join us</a> on Day 2 (Sept 16) of <b><span style="color: #f1c232;">DVCon India 2016</span></b> at Leela Palace, Bangalore to attend this
keynote and other exciting topics.</span><br />
<span style="font-family: "verdana" , sans-serif;"><br /></span>
<span style="font-family: "verdana" , sans-serif; font-size: x-small;"><i>Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”</i></span></div>
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</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com2tag:blogger.com,1999:blog-9157206405178843096.post-55922159455024554512016-08-27T12:32:00.000+05:302016-09-09T10:22:11.467+05:30Quick chat with Wally : Keynote speaker, DVCon India 2016<div dir="ltr" style="text-align: left;" trbidi="on">
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<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: right; margin-left: 1em; text-align: right;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiiBGgSs9upYNv-yIhDIjxnyi1Mo99pbZIttoPTDduBsamGq3ZfPCNM5KKMYuRtkeEeGhD2lZJPAPcbm1vhFVJpzTHJpCp10Tb4F2-Is5PLvutNwnWioixnZK99E2oUXN9Tz17I7E8Bid8/s1600/wrhines_hirez+2015.jpg" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiiBGgSs9upYNv-yIhDIjxnyi1Mo99pbZIttoPTDduBsamGq3ZfPCNM5KKMYuRtkeEeGhD2lZJPAPcbm1vhFVJpzTHJpCp10Tb4F2-Is5PLvutNwnWioixnZK99E2oUXN9Tz17I7E8Bid8/s200/wrhines_hirez+2015.jpg" width="163" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i>Walden C. Rhines</i></td></tr>
</tbody></table>
<span style="font-family: "verdana" , sans-serif;"><i>It takes a
village to raise a child!</i> Correlating it with the growth of an engineer, YES!
it does require <b>Contribution</b> from many & <b>Collaboration</b> with many. While our
respective teams play the role of a family, the growth is accelerated when we <b>Connect</b>
beyond these boundaries. DVCon India is one such platform to enable all of
these for Design, verification & ESL community. The 3<sup>rd</sup> edition
of <a href="https://dvcon-india.org/">DVCon India</a> is planned on September 15-16 at Leela Palace, Bangalore. <o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">The
opening <a href="https://dvcon-india.org/content/event-details?id=205-50">keynote</a> on Day 1 is from <a href="https://www.mentor.com/company/executive_team/w_rhines">Walden C. Rhines</a>, CEO & Chairman, Mentor
Graphics. It is always a pleasure to hear his insights on the Semiconductor
& EDA industry. This year, he picked up an interesting topic – <span style="color: #f1c232;">“Design Verification:
Challenging Yesterday, Today and Tomorrow”</span>. While we all wait with
excitement to hear him on Sept 15, Wally was kind enough to share his thoughts
on some queries that came up after I read the brief about his keynote. Below is
an unedited version of the dialogue for you.<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">Wally your
keynote topic is an excellent start to the program discussing the challenges
head on. Tell us more about it?</span></span></div>
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<span style="font-family: "verdana" , sans-serif;">Our industry has done a remarkable
job of addressing rising complexity in terms of both design and verification
productivity. What’s changed recently in verification is the emergence of a new
set of requirements beyond the traditional functional domain. For example, we
have added clocking, power, performance, and software requirements on top of
the traditional functional requirements; and each of these new requirements
that must be verified. While a continual development of new standards and
methodologies has enabled us to keep pace with rising complexity and be
productive, we are seeing that requirements for security and safety are
becoming more important and could ultimately pose challenges more daunting than
those we have faced in the past.<o:p></o:p></span></div>
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<br /></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">In the last
few years ESL adoption has improved a lot. Is it the demand to move at higher
abstraction level or convergence of diverse tool sets into a meaningful flow
that is driving it?</span><o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Actually, a little of both.
Historically, our industry has addressed complexity by raising abstraction when
possible. For example, designers now have the option of using C, SystemC, or
C++ as a design entry language combined with high-level synthesis to
dramatically shorten the design and verification cycle by producing correct-by-construction,
error-free, power-optimized RTL. <o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Moving beyond high-level synthesis,
we are seeing new ESL design methodologies emerge that allow engineers to
perform design optimizations on today’s advanced designs more quickly,
efficiently, and cost-effectively than with traditional RTL methodologies by
prototyping, debugging, and analyzing complex systems before the RTL
stage. ESL establishes a predictable, productive design process that
leads to first-pass success when designs have become too massive and complex
for success at the RTL stage.<o:p></o:p></span></div>
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<br /></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">The rise
of IoT is stretching the design demands to far ends i.e. server class vs edge
node devices. How does the EDA community view this problem statement?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Successful development of today’s
Internet of Things products involves the convergence of best practices for
system design that have evolved over the past 30 years. However, these
practices were historically narrowly focused on specific requirements and
concerns within a system. Today’s IoT ecosystems combine electronics, software,
sensors, and actuator; where all are interconnected through a hierarchy of
various complex levels of networking. At the lowest level, the edge node as you
referred to it, advanced power management is fundamental for the IoT solution
to succeed, while at the highest-level within the ecosystem, performance is
equally critical. Obviously, EDA solutions exist today to design and verify
each of these concerns within the IoT ecosystem. Yet more productivity can be
achieved with more convergence of these solutions when possible. For
example, there is a need today to eliminate the development of multiple silos
of verification environments that have traditionally existed across various
verification engines—such as simulation, emulation, prototyping, and even real
silicon used during post-silicon validation. In fact, work has begun with
Accellera to develop a Portable Stimulus standard which will allow engineers to
specify the verification intent once in terms of stimulus and checkers, which
then can be retargeted though automation for a diverse set of verification
engines.<o:p></o:p></span></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">Wally you
seem to love India a lot! We see frequent references from you about the growing
contribution of India to the global semiconductor community. Any specific
trends that you would like to highlight?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">Perhaps one of the most striking
findings from our 2016 Wilson Research Group Functional Verification Study is
how India is leading the world in terms of verification maturity. We can measure
this phenomenon by looking at India’s adoption of System Verilog and UVM
compared to the rest of the world, as well as India’s adoption of various
advanced functional verification techniques, such as constrained-random
simulation, functional-coverage, and assertion-based techniques.<o:p></o:p></span></div>
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<br /></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">This is
the 2nd time you would be delivering a keynote at DVCon India. What are your
expectations from the conference?<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;">I expect that the 2016 DVCon India
will continue its outstanding success as a world-class conference, growing in
both attendance and exhibitor participation, while delivering high-quality
technical content and enlightening panel discussions.<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="color: #f1c232;">Thank you Wally! We look forward to
see you at <a href="https://dvcon-india.org/">DVCon India 2016</a>.</span><o:p></o:p></span></div>
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<i style="font-family: verdana, sans-serif;"><span style="font-size: x-small;">Disclaimer: “The postings on this blog are my own and not necessarily reflect the views of Aricent”</span></i></div>
</div>
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<span style="font-family: "verdana" , sans-serif;">On our return after watching ‘Finding Dory’, my son asked, “Dad, if you were to find Dory would you be able to do that”? I said, “Ofcourse”! Next, came HOW? I reminded him that my job is to <a href="http://whatisverification.blogspot.in/2016/06/learning-verification-with-angry-birds.html">Find Bugs</a> and so I know the tricks of the game already. That made him super excited and wanting to know more about it. Given that this time the reference was picked by him, I decided to continue the same to explain him further.</span></div>
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<span style="font-family: "verdana" , sans-serif;">In the movie, Marlin and Nemo were finding Dory inside the Marine Life Institute (MLI), likewise, we find bugs inside the design called as <span style="color: #f1c232;"><b>System on Chip (SoC)</b></span>. The SoC has a lot of similarity to MLI in the sense that it is big and complex. As MLI had different sections, our SoC has different blocks where Dory (Bug) can be found. Also it is not only the sections but the inter-connections that are equally important. When we look for Dory (Bug) inside these blocks we call it <b><span style="color: #f1c232;">IP verification</span></b> and when our focus is on the inter-connections we call it <span style="color: #f1c232;"><b>Integration or SoC Verification</b></span>.</span></div>
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<span style="font-family: "verdana" , sans-serif;"><span style="font-size: x-small;"><i>Image Source : http://www.socwall.com/desktop-wallpaper/7462/dory-and-marlin-by-ryone/</i></span></span></div>
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<span style="font-family: "verdana" , sans-serif;">We start off our quest using the <span style="color: #f1c232;"><b>Marlin way</b></span> i.e. “Assess the situation, evaluate, and plan it out”. We call it the <span style="color: #f1c232;"><b>Directed Verification</b></span> approach wherein we understand the design, prepare a plan on where and how we would look around for Dory (Bug) and then execute accordingly. During this process we also keep asking (reviews) around (designers & peers) to let us know if we are missing out on anything. So if Dory is somewhere around, there is a chance we may sight her. But since Dory doesn’t think much before acting, that makes her unpredictable. There is always a possibility that we may not find her as per our plan.</span></div>
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<span style="font-family: "verdana" , sans-serif;">My son’s eyeballs zoomed…. THEN?</span></div>
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<span style="font-family: "verdana" , sans-serif;">Then we also do what Marlin & Nemo did i.e. follow “What would Dory do”? My son jumped, "She wouldn’t think twice and be random". Yes! We pick the <span style="color: #f1c232;"><b>Dory way</b></span> and we call it <span style="color: #f1c232;"><b>Random Verification</b></span>. We search randomly everywhere in an unplanned sequence and guess what? The chances that we would find Dory (Bug) increase. To make it more effective, we define weights and constraints to the randomness so as to improve our luck of finding her further. The approach now becomes <b><span style="color: #f1c232;">Constrained Random Verification</span></b> (<a href="http://whatisverification.blogspot.in/2013/05/constrained-random-verification-flow.html">CRV</a>). While following this random pattern we also take a note (coverage) of where all we have visited to avoid repeating same place again and save time. Now we can find her faster. Tracking coverage on top of CRV is called <span style="color: #f1c232;"><b>Coverage Driven Verification</b></span> (CDV). So if we missed finding Dory (Bug) using the Marlin way (Directed verification) we still have an option to find her the Dory way (CRV).</span></div>
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<span style="font-family: "verdana" , sans-serif;">That settled my son for a while till he pointed again saying, “Dad, maybe you should seek help from Bailey, the beluga whale who can find Dory faster than anyone using echo location”. I smirked and told him that we have our Bailey too and we call it <span style="color: #f1c232;"><b>Formal Verification</b></span>. But then, Bailey was dependent on the whale voice between Dory & Destiny, the whale shark without which he couldn’t be of much help. Similarly, in Formal we are dependent on the assertions that connect the tool to the bug in the design. The effectiveness of this approach is purely dependent on the quality of voice (assertions) and the connect (covering all parts of design) between Dory & Destiny. But yes, if that is in place, it is really fast & effective.</span></div>
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<span style="font-family: "verdana" , sans-serif;">Now convinced that his dad would be able to find Dory, my son asked, “So once you have found Dory, what do you do next”?</span></div>
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<br /></div>
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<span style="color: #f1c232; font-family: "verdana" , sans-serif;">I laughed and told that we don’t have to find only 1 Dory (Bug). There are many of them and the address and architecture of the institute (new SoC) also keeps changing. So we just keep Finding Dory (Bug)!!!</span></div>
<div style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif; font-size: x-small;"><i>Disclaimer: "The postings on this blog are my own and not necessarily reflects the views of Aricent"</i></span></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com10tag:blogger.com,1999:blog-9157206405178843096.post-77406504348545040782016-06-12T11:37:00.000+05:302016-10-02T21:10:53.321+05:30Learning Verification with Angry Birds<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-family: "verdana" , sans-serif;">What do you say when your little one asks you, “Dad! What do
you do”? Well I said, “I am an engineer”. For his age, he knew who is a driver,
a doctor and a policeman. So the next question was “What does an engineer do”?
I pointed him to different man made stuff around to explain him what all an
engineer does. As an inquisitive kid he wanted to know if I build them all.
That is when I tried to explain different engineering functions building different artifacts. So the question came back as to, “What do you do”? Finally,
I told him that, “<span style="color: #f1c232;"><b>I find BUGS in the designs</b></span>”. The next one was HOW? Given that
he watched The Angry Bird movie recently & loves to play that game so I
picked from there to explain what a verification engineer really does.<o:p></o:p></span></div>
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<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjocY-f5tINvX7nTMlpARDbq8TQmYZGLuuVk43kBkPxCi1EotfQ9OzOwAD88q5qyT8ovGtPPR4MpxsQGMNQ-xp0HJaQzTmzFtWcoDP-upOMHaxUErnBKmGcNh0ZsCVieYd_XyUDMOCNVGY/s1600/Picture2.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="376" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjocY-f5tINvX7nTMlpARDbq8TQmYZGLuuVk43kBkPxCi1EotfQ9OzOwAD88q5qyT8ovGtPPR4MpxsQGMNQ-xp0HJaQzTmzFtWcoDP-upOMHaxUErnBKmGcNh0ZsCVieYd_XyUDMOCNVGY/s640/Picture2.png" width="640" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i style="font-size: 12.8px;">Figure 1 : Labeled screenshot of The Angry Birds game </i></td></tr>
</tbody></table>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">As in the figure above, the screenshot of the game is called
<b><span style="color: #f1c232;">TESTBENCH</span></b> for us. The target that is seen on the right is called the <b><span style="color: #f1c232;">DESIGN
UNDER TEST</span></b> or DUT in short. Our goal is to hammer the DUT with minimum
iterations such that all the BUGS inside it like the pigs above get kicked out.
On the left you see a series of angry birds waiting to take the leap. We refer
to them as the PACKETS or <b><span style="color: #f1c232;">SEQUENCE ITEMS</span></b>. They are all from the same base class
“<i>angry_birds</i>” i.e. have certain characteristics in common while some different
features in each one so as to ensure we hit the DUT differently. We sequence
these birds (sequence items) in such a way so as to generate different
scenarios to weed out the pigs (bugs). This scenario is called a <b><span style="color: #f1c232;">TEST CASE</span></b>. The
catapult shown is known as the <b><span style="color: #f1c232;">DRIVER</span></b> in our testbench. It takes the angry bird
(sequence item) and throws (drives) it on to the DUT at different points known
as <b><span style="color: #f1c232;">INTERFACES</span></b> of the DUT. </span><span style="font-family: "verdana" , sans-serif;"> </span><span style="font-family: "verdana" , sans-serif;">Once the angry
bird (sequence item) hits the DUT, there is an inbuilt <b><span style="color: #f1c232;">MONITOR</span></b> in the game (testbench)
that confirms if the flight taken is useful or not & if it is, how much? If the hit resulted in correct outcome the <b><span style="color: #f1c232;">SCOREBOARD</span></b> gives a go ahead and this leads to the scores that we get and we call it <span style="color: #f1c232;"><b>COVERAGE</b></span>. The high score is
the maximum coverage achieved with this test case. </span><span style="font-family: "verdana" , sans-serif;"> </span><span style="font-family: "verdana" , sans-serif;">When we are able to kill all the pigs (here bugs)
hidden in different parts of the DUT, we are all set to move to another screen
i.e. new test case targeting another part of the DUT. Once all tests at a given
level pass, we move to the next level which is a little tougher. We can call it
moving vertically i.e. block to subsystem to SoC/Top OR moving horizontally
within a given scope i.e. more complex test scenarios or stress tests. Usually
when we have passed all levels, by that time another version of the game is
released and we move to that one i.e. next <b><span style="color: #f1c232;">PROJECT</span></b>.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;">After explaining it to my son, I felt he would be fascinated
with my work. He thought about it and said, “Dad, so you don’t really work, you
go to office and play”!!! <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: "verdana" , sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="color: #f1c232; font-family: "verdana" , sans-serif;">All I could tell him was, “Become a Verification
Engineer and you can play too at work”!!!</span><br />
<span style="color: #f1c232; font-family: "verdana" , sans-serif; font-size: x-small;"><i style="color: black;"><br /></i></span><span style="color: white; font-family: "verdana" , sans-serif; font-size: xx-small;"><i>Disclaimer: "The postings on this blog are my own and not necessarily reflects the views of Aricent"</i></span></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com10tag:blogger.com,1999:blog-9157206405178843096.post-7946945530456577732016-05-23T19:55:00.000+05:302016-05-23T19:55:25.306+05:30.....of Errors & Mistakes in Verification<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Miniaturization of devices has led to packing more
functionality on the given slice of silicon. An after effect of that is heating
of the device due to increased power consumption and discovering innovative
ways of cooling off these components. As electronics adopted wireless, the
concern on power came to forefront as, who wants to recharge the battery every
second hour. Different techniques have been adopted since then to address this
growing concern. One such technique is letting parts of silicon go to into
hibernation and trigger a wake up when needed. My hibernation from blogging was
no different except that though I received many pokes during this time probably
the trigger wasn’t effective enough to tantalize the antennas of the blogger in
me. It was only during a recent verification event hosted by Mentor Graphics
when my friend Ruchir Dixit, Technical Director – India at Mentor Graphics introduced
the event with an interesting thought touching the basics of verification. The
message completely resonates the idea of this blog of exploring verification
randomly but rooted on basics and I took it as a sign to get the ball rolling
again. To start with, I am sharing the thoughts that actuated this restart.
Thank you Ruchir for allowing me to share the same.<o:p></o:p></span></div>
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<br /></div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgzwuyPAhje4Za12tywjK_6TX2qmcrZUdwp1GlbcDk5MQwX_0SJMOkAQYe-KMXoL4COmvwiA5ph4nW9wqp_JbLKM8Gl7M7wb56pbt6DysvzLAeR1S3o8uGFzz03HwO4pTyi2aDuZOpz7BE/s1600/log4.png" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="286" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgzwuyPAhje4Za12tywjK_6TX2qmcrZUdwp1GlbcDk5MQwX_0SJMOkAQYe-KMXoL4COmvwiA5ph4nW9wqp_JbLKM8Gl7M7wb56pbt6DysvzLAeR1S3o8uGFzz03HwO4pTyi2aDuZOpz7BE/s640/log4.png" width="640" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><i>Source: Slides from Ruchir Dixit - 'Verification Focus & Vision' presented at Verification Forum, Mentor Graphics, India</i></td></tr>
</tbody></table>
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<span style="text-align: left;"><br /></span></div>
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</div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Before we unfold the topic further have you ever thought as
to why computers only spell out ERRORS & not MISTAKES?</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Let’s start with understanding the basic difference between an
error & a mistake. A mistake is usually a choice that turns out to be
wrong because the outcome is wrong. Mistakes are made when a free choice
is made either accidentally or performance based but can be prevented or
corrected. An error, on the other hand, is a violation of a golden reference or
set of rules that would have lead to a different action and outcome. Errors typically are a result of
lack of knowledge and not choice. That is the reason that computer doesn’t make
mistakes and only throws error on screen when unable to move forward on a
pre-defined set of actions or sees a violation to them. And that is again a
reason why you see Warnings & Errors from our EDA tools and not Mistakes :) Machines don’t make
mistakes… we do!<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Now talking about verification, the sole reason of why we
verify is <b><span style="color: #f1c232;">BUGS!</span></b> And the source of these BUGS are the <b><span style="color: #f1c232;">ERRORS</span></b> & <b><span style="color: #f1c232;">MISTAKES</span></b>
committed as part of code development. <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Mistakes as we understood earlier is resultant of a free
choice. While no one wants to make a bad choice, still this creeps into the
code due to distractions or coding in a hurry. To prevent or correct such
mistakes it is the basic discipline one needs to follow and that is where the
EDA tools come to rescue in assisting you to make the right choice.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"> <o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Errors typically happen due to ignorance about the subject
or partial knowledge leading to wrong assumptions. This could further
find it roots in incomplete documentation or incorrect understanding of the
subject. Given that documentation & the resulting conclusions are more
subjective it is hard to define the right way to document anything. The only
way to minimize errors is to prevent them from occurring by defining clear set
of rules that need to be followed and that is where ‘Methodology’ comes into
picture. A classic example of the same is having a template generator for UVM
code to ensure the code is correct by construction & integrates seamlessly
at different levels. Having coding guidelines is another way to reduce errors.
Uncovering the rest of the errors is where the tests become important and unless
we stimulate that scenario we may not know what & where the error is.<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">So while errors & mistakes are unavoidable, <span style="color: #f1c232;">it is the
deployment of the right set of methodologies and tools that leads to a <b>bug free
silicon …. In time…. Every time!</b></span><o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><span style="color: #f1c232;"><b><br /></b></span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">After writing this post, I was tempted to say that <span style="color: #f1c232;"><i>‘To ERR is
HUMAN and to FORGIVE or VERIFY is DIVINE!</i></span> </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">But then that would be a MISTAKE again :)<o:p></o:p></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><span style="color: #e69138;">Happy Bug Hunting!!!</span><o:p></o:p></span></div>
<div style="text-align: left;">
</div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif; font-size: x-small;"><i>Disclaimer: “The postings on this blog are my own and not
necessarily reflect the views of Aricent”</i></span><o:p></o:p></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com0tag:blogger.com,1999:blog-9157206405178843096.post-87453564756064161002015-10-18T16:32:00.000+05:302015-10-18T16:36:28.896+05:30The magical chariot in verification!<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;">As the holiday season kicked off in India, the antennas of
my brain tickled to intercept between what is going around and relate it to
verification. In past, I have made an attempt to correlate off topic subjects
with verification around this time every year. Dropping the mainstream
sometimes helps as it gives you a different perspective and a reason to think
beyond normal, to think out of the box, to see solutions in different context
and apply it to yours, in this case verification! The problem statement being –
<span style="color: #f1c232;">driving verification closure with growing complexity and shrinking schedules.</span></span></div>
<div style="text-align: justify;">
</div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Before I move forward, let me share the context of these holidays.
This is the time in India when festivities are at their peak for few weeks.
Celebration is in the air and the diversity in the culture makes it even more fascinating.
People from all over India celebrate this season and relate it to various
mythological stories while worshipping different deities. The common theme
across is that in the war of good and evil, good prevails finally! What is
interesting though are the different stories associated with each culture
detailing these wars between good and evil. In the process of growth of the
evil and the evolution of good to fight it, both tend to acquire different
weapons to attack as well as defend. And when the arsenal at both ends is
equally equipped, the launch-pad becomes a critical factor in arriving to a
decision. Possibly, that is another reason why different deities ride different
animals and some of these stories talk about those magical chariots that kind
of made the difference to the war. </span></div>
<div style="text-align: justify;">
</div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;">So how does this relate to verification?</span></div>
<div style="text-align: justify;">
</div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">As verification engineers our quest with bugs amidst growing
complexity has made us acquire different skills. We started off with directed
verification using HDLs/C/scripts and soon moved to Constrained random
verification. Next we picked different coverage metrics i.e. functional, code
coverage and assertions. As we marched further, we added formal apps to take
care of the housekeeping items that every project needs. Almost a new tool/flow
keeps adding every couple of years in line with the Moore’s law <span style="font-family: Wingdings; mso-ascii-font-family: Calibri; mso-ascii-theme-font: minor-latin; mso-char-type: symbol; mso-hansi-font-family: Calibri; mso-hansi-theme-font: minor-latin; mso-symbol-font-family: Wingdings;"><span style="mso-char-type: symbol; mso-symbol-font-family: Wingdings;">J</span></span>. And now if we look
back, the definition of verification as a non-overlapping concern (functional
only) in the ASIC design cycle few decades ago is all set to cross roads with
the then perceived orthogonal concerns (clock, power, security and software).
While we continue to add a new flow, tool or methodology for each of these
challenges that are rocking the verification boat, what hasn’t changed much in
all these years is the platform that the verification teams continue to use.
Yes, new tools and techniques are required but are these additions bringing the
next leap that is needed or are they just coping up with the task at hand? Is it
time to think different? Time to think beyond normal? Time to think out of the
box? And if YES what could be a potential direction?</span><br />
<span style="font-family: Verdana;"></span> </div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">This is where I come back to the mythological stories
wherein when the arsenal wasn’t enough; it was the magical chariot that did the
trick! Yes, maybe the answer lies in bringing the change in the platform – our <span style="color: #f1c232;">SIMULATORS</span>
<span style="color: #f1c232;">– the workhorse of verification!</span> Interestingly, the answers do not need to be
invented. There are alternate solutions available in form <span style="color: #f1c232;">VIRTUAL PROTOTYPING<strong>
</strong></span>or using <span style="color: #f1c232;">HARDWARE ACCELERATORS/EMULATORS</span> for RTL simulations. Adopting these
solutions would give an edge on both the bugs causing menace as well as the
competition! And for those who think it is costly to adopt, a lost market
window for the product could be even costlier!!! </span></div>
<div style="text-align: justify;">
</div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">As <a href="http://dvcon-india.org/conf/keynote-harry-foster/">Harry Foster</a> mentioned in his keynote at <a href="http://www.dvcon-india.org/">DVCon India 2015</a>
– It’s about time to bring in the paradigm shift from <em><span style="color: #f1c232;">“Increasing cycles of
verification TO maximising verification per cycles”</span></em>. He also quoted Henry Ford,
the legend who founded Ford Motor Company and revolutionized transportation and
American industry.</span></div>
<div style="text-align: justify;">
</div>
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<span style="font-family: Verdana, sans-serif;">
</span></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZZ7Rn2ZezwkpfoQJNS9rCukFXJxwzsTns85m7L6Fbd2QJoTq-DTewyacdhtSAe0YZK_cUNEVmBkz-sENvUn08L-uQA7R8A6f0KlsQteSvwnbwCt15XZt-UmaC8FH75v8vcvdcibytlPU/s1600/henry.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="480" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZZ7Rn2ZezwkpfoQJNS9rCukFXJxwzsTns85m7L6Fbd2QJoTq-DTewyacdhtSAe0YZK_cUNEVmBkz-sENvUn08L-uQA7R8A6f0KlsQteSvwnbwCt15XZt-UmaC8FH75v8vcvdcibytlPU/s640/henry.jpg" width="640" /></a></div>
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</div>
<div class="MsoNormal" style="margin: 0cm 0cm 10pt; text-align: justify;">
<o:p><span style="font-family: Verdana, sans-serif;">On that note, I wish you all a </span></o:p><span style="color: #f1c232; font-family: Verdana, sans-serif;">Happy Dussehra!!! Happy Holidays!!!</span><br />
<br />
<br />
<span style="color: #f1c232; font-family: Verdana;">If you liked this post you would love -</span><br />
<span style="font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2011/10/mythology-verification.html">Mythology & Verification</a></span><br />
<span style="font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2012/10/hanuman-of-verification-team.html">HANUMAN of verification team!</a></span><br />
<span style="font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2013/10/trishool-for-verification.html">Trishool for verification</a></span><br />
<span style="font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2014/10/verification-and-firecrackers.html">Verification and firecrackers</a></span></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com2tag:blogger.com,1999:blog-9157206405178843096.post-25720790828886366872015-09-25T22:05:00.000+05:302015-09-25T22:05:21.172+05:30DVCON India turned 2!!!<div dir="ltr" style="text-align: left;" trbidi="on">
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<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;">Nothing beats nurturing a seed, an infant, an idea or an
EVENT; watching it grow and clocking milestones of its achievements. For many
of us, the bright sunny day of Sept 10 bought the same feeling. Yes, this month <span style="color: #f1c232;">DVCon
India turned 2</span><span style="color: #f1c232;">!</span> </span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhXd9aaRL4pMQbcFwPIeYIbAO960wYZZ3o5ipWe-nUFVRr45Mr1ueqw6KOZ3tC-scMDHjokQ9t2Ion6SfGIVWYRDhAGJ6nLx3t-cH0EO0ZV7rcIoqzLV84al_wFVL-99yJTOKpTV6yDVuE/s1600/DVcon+India.JPG" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" height="212" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhXd9aaRL4pMQbcFwPIeYIbAO960wYZZ3o5ipWe-nUFVRr45Mr1ueqw6KOZ3tC-scMDHjokQ9t2Ion6SfGIVWYRDhAGJ6nLx3t-cH0EO0ZV7rcIoqzLV84al_wFVL-99yJTOKpTV6yDVuE/s320/DVcon+India.JPG" width="320" /></a></div>
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<span style="font-family: Verdana, sans-serif;">Sponsored by <a href="http://www.accellera.org/">Accellera</a>, the conference expanded to
India last year. An excellent platform for the design and
verification community working at IP, SoC and System level to discuss problems,
alternate solutions and contribute to standards. The ecosystem today has multiple EDA driven
forums showcasing the right and optimal usage of their respective tools. DVCon being
vendor neutral focuses on the need for standards in languages and
methodologies to overcome the challenges introduced by rising complexity while emphasizing
the right way of applying these standards.</span></div>
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<span style="color: #f1c232; font-family: Verdana, sans-serif;"><strong>History of DVCon</strong></span></div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;">The history of DVCon can be traced back to late 80s when
VHDL users met twice a year under the name VUG. By early 90s, it became an
annual event called VIUF. Around the same time Verilog users also gathered
annually for IVC. In the late 90s, these two events joined hands for
HDLCon. In 2003, it was re-branded as DVCon. Based on these facts, <a href="http://www.dvcon.org/">DVCon US</a>
actually has been serving the community for 25+ years. In 2014, it expanded
globally to <a href="http://www.dvcon-india.org/">India</a> & <a href="http://www.dvcon-europe.org/">Europe</a>.</span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjxadxdy6mftH84Z3teazwB-LXudQlyXa4OpqwuogIs4la7yfzIpO-yk7wuCX7FLxstB-DxHsB-p2vdzYHL-rHtkETWcp7NvbN9pXoyfdegCZLe_LNGoxR83pojQvELKrXQmMmg7ZauPWk/s1600/dv2.png" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="202" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjxadxdy6mftH84Z3teazwB-LXudQlyXa4OpqwuogIs4la7yfzIpO-yk7wuCX7FLxstB-DxHsB-p2vdzYHL-rHtkETWcp7NvbN9pXoyfdegCZLe_LNGoxR83pojQvELKrXQmMmg7ZauPWk/s640/dv2.png" width="640" /></a></div>
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<span style="font-family: Verdana, sans-serif;">The 2 day conference was held at Leela Palace, Bangalore on
Sept 10-11 2015. Riding on the success of <a href="http://dvcon-india.org/archive/2014/">DVCon India 2014</a>, this year was
planned to be bigger and better!!! Change in venue, modified program for higher
interaction among the participants, addition of Gala dinner and higher
quality of the content were the key highlights of this year’s event. <span style="mso-spacerun: yes;"> </span>The program was put together keeping in mind
the <span style="color: #f1c232;">4Cs : Contribute, Collaborate, Connect & Celebrate <strong>-</strong></span> a clear reflection
of spirit of DVCon.</span></div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="color: #f1c232; font-family: Verdana, sans-serif;"><strong>DAY 1</strong></span></div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;">Packed hall with ~600 participants witnessing the lamp lightning
ceremony was a clear indication of the enthusiasm that was set to unfold. Yours
truly opened the DAY 1, introducing the program underlining the message
that <span style="color: #f1c232;">DVCon is all about active participation!</span> <a href="http://dvcon-india.org/conf/keynote-harry-foster/">Harry Foster</a> from <a href="http://www.mentor.com/">Mentor Graphics</a>
delivered the opening keynote <span style="color: #f1c232;">'</span><span style="color: #f1c232;">From Growing Complexity to Faster Horses'</span> citing
interesting facts about the trends in design and verification. <a href="http://dvcon-india.org/conf/keynote-vinay-shenoy/">Vinay Shenoy </a>shared
an excellent insight as part of the invited keynote <span style="color: #f1c232;">'Perspective on Electronics
Ecosystem in India'</span> covering the history and initiatives under ‘Make in India’
campaign. Rest of the day kept everyone busy with invited talks from subject
matter experts, panels on upcoming technologies and tutorials around standards.
The exhibitors kept the crowd involved all throughout sharing potential solutions
to the challenges faced. Having drenched with
a rich rain of technical content throughout the day, it was time for some fun
in the evening. The crowd came together celebrating <span style="color: #f1c232;">10 years of System Verilog</span>
as a standard and <span style="color: #f1c232;">IEEE standardization of UVM</span>. Amidst applauses, pranks, music,
dance and illusions, the day 1 concluded with tweets and chirping over dinner
& drinks.</span></div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="color: #f1c232; font-family: Verdana, sans-serif;"><strong>DAY 2</strong></span></div>
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<strong><span style="color: #e69138; font-family: Verdana;"></span></strong> </div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;">An extended DAY 1 didn’t stop the participants to change the
gears back to technical on DAY 2 with Ajeetha Kumari opening the day followed
by Dennis Brophy sharing an overview on Accellera. <a href="http://dvcon-india.org/conf/keynote-manoj-gandhi/">Manoj Gandhi</a> from <a href="http://www.synopsys.com/">Synopsys</a> delivered the
opening keynote <span style="color: #f1c232;">'Propelling the Next Generation of Verification Innovation'</span>
discussing how design and verification challenges have progressed and the need of the hour. <a href="http://dvcon-india.org/conf/keynote-atul-bhatia/">Atul Bhatiya</a> took the stage next as an invited keynote
speaker talking about <span style="color: #f1c232;">'Opportunities in Semiconductor Design in India'</span>, encouraging the audience to envision and jump where the ball would be rather
than running after it. Rest of the day hosted different tracks on papers and
posters shortlisted by the Technical Program committee. By the evening,
overwhelmed with the discussions, solutions and networking opportunities, the
junta assembled again to appreciate the efforts put in by members of the <a href="http://dvcon-india.org/about/sub-committees/">DVCon India committees</a> and congratulate the winners of <a href="http://dvcon-india.org/awards/">Best Paper & poster awards!</a></span></div>
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</span></div>
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<span style="font-family: Verdana, sans-serif;">As the Day 2 concluded, the <a href="http://dvcon-india.org/about/steering-committee/">team</a> that put in stretched hours
for almost a year was overjoyed with the grand success of the event. Those relentless
efforts paid well in bringing up the conference to the next level. Yes! The nurturing
all these days, witnessing the growth and marking the achievement of DVCon India
2015 was all worth it!</span></div>
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<span style="font-family: Verdana, sans-serif;">
<span style="color: #f1c232;">Other posts on DVCon India -</span></span></div>
<div style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2014/07/dvcon-goes-global.html">DVCON goes GLOBAL!</a></span></div>
<div style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2014/09/dvcon-india-journey-of-verification.html">DVCON India : Journey of Verification (preview)</a></span></div>
<div style="text-align: justify;">
<span style="color: #f1c232; font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2014/10/dvcon-india-2014-event-recap.html">DVCON India 2014 : Event Recap!</a></span></div>
<div style="text-align: justify;">
<span style="font-family: Verdana;"><a href="http://whatisverification.blogspot.in/2015/02/dvcon-enabling-os-of-ooda-loop-in-dv.html">DVCON : Enabling the O's of OODA loop in DV</a></span></div>
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<o:p><span style="font-family: Verdana, sans-serif;"> </span></o:p></div>
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<span style="font-family: Verdana, sans-serif;">
</span></div>
</div>
<div class="blogger-post-footer"><a href="https://twitter.com/share" class="twitter-share-button" data-via="gjalan">Tweet</a>
<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com2tag:blogger.com,1999:blog-9157206405178843096.post-68737727905344364572015-08-11T11:54:00.001+05:302015-08-11T11:54:08.430+05:30101 with Richard Goering : The technical blogging guru<div dir="ltr" style="text-align: left;" trbidi="on">
<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: right; margin-left: 1em; text-align: right;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjlV1Qb-o1B6uxPgCCuhSULH9I6PoB6zF58TyVnOgPV4hum5yNjd2hGTcsAYor6B3NyYg5DoZ706OHAflQxNcgmXmtpqoiCl-lXCTmHT4OivDWt6qkuLMOQBWKZHi0zxqNFMJk8U8P3SNA/s1600/Goering1.jpg" imageanchor="1" style="clear: right; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjlV1Qb-o1B6uxPgCCuhSULH9I6PoB6zF58TyVnOgPV4hum5yNjd2hGTcsAYor6B3NyYg5DoZ706OHAflQxNcgmXmtpqoiCl-lXCTmHT4OivDWt6qkuLMOQBWKZHi0zxqNFMJk8U8P3SNA/s200/Goering1.jpg" width="200" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="font-family: Verdana, sans-serif; font-size: xx-small;">Richard Goering - retired EDA editor</span></td></tr>
</tbody></table>
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<span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"><span style="font-family: Verdana, sans-serif;">The
digital world has connected people across geographies without in person meeting
or talking. It is interesting to see the cross pollination of ideas, thoughts
and mentoring that travels across boundaries flying on the wings of this
connected world. The bond developed when connected on these platforms is no
less than a real one. I happen to have a similar bond with Richard Goering as a
religious follower of his technical articles for more than a decade. So when
Richard announced his retirement, I requested him for an interview to be
published on this blog. Humble as he is all these years, he accepted this request
and what follows is a short interview with the blogging guru whom I admire a
lot for his succinct yet comprehensive posts all these years.</span></span></div>
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<span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"></span> </div>
<div style="text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="color: #f1c232; font-family: Verdana, sans-serif;"><strong>Q: Richard,
please share a brief introduction to your career?</strong></span></span></div>
<div style="text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div style="text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">I have
always been a writer. I graduated from U.C. Berkeley with a degree in
journalism in 1973. In 1974, living in what was to become Silicon Valley, I worked
for a long-dead publication called Northern California Electronics News. I
wrote an article that described electron beam lithography as the “next big
thing” in semiconductor manufacturing. Today this technology is still emerging.
</span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">In the
early 1980s I was a technical writer in Kansas City, Missouri for a company
that made computer-controlled bare board testers. I took classes at the
University of Missouri in Fortran, Pascal, and assembly language. I still
remember going to the campus computer centre with a stack of punched cards,
hoping that one error wouldn’t keep the whole program from compiling. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">In
1984 I joined the staff of Computer Design magazine, and wrote several articles
about test. Shortly afterwards I was asked to go cover a new area called “<strong><span style="color: #e69138;">CAE</span></strong>”
(computer-aided engineering). This was, of course, the discipline that became
“<strong><span style="color: #e69138;">EDA</span></strong>” and I have written about it ever since. I was the EDA editor for Computer
Design (4 years) and then for EE Times (17 years). I worked for Cadence,
primarily as a blogger, for the past 6 years. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="color: #f1c232; font-family: Verdana, sans-serif;"><strong>Q: When
did you realize it’s time to start blogging and why?</strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">I
actually had a blog during my final years at EE Times, which ended in 2007. At
Cadence I wrote the <a href="http://community.cadence.com/cadence_blogs_8/b/ii/">Industry Insights</a> </span><span style="font-family: Verdana, sans-serif;">blog. Today there are few traditional publications left,
especially in print, and <span style="color: #f1c232;"><span style="color: white;">it appears that blogs are a primary source of
information for design and verification engineers.</span> </span></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Q: What
are the three key disruptive technologies you observed that had a high impact
on the semiconductor industry?</span> </strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">From
an EDA perspective, the most significant change was the move from <span style="color: white;">gate-level
schematics to RTL design</span> with VHDL or Verilog. This move provided a huge leap
in productivity. It also allowed verification engineers to work at a higher
level of abstraction. </span></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">Looking
more closely at verification, there was a shift from <span style="color: white;">directed testing to constrained-random
test generation</span>. This came along with coverage metrics, executable verification
plans, and languages such as “e” from Verisity. I think a third disruptive
technology is emerging just now – it’s the importance of software in SoC
design, and the need for <span style="color: white;">software-driven verification</span>. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span style="font-family: Verdana;"><strong><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="color: #f1c232;">Q: </span></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="color: #f1c232;">When
did you start hearing the need for a verification engineer in the ASIC design
cycle?</span> </span></strong></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span style="font-family: Verdana;"><strong><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span></strong></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">I
think this goes back many years. Most chip design companies have separate
verification teams. Nowadays there’s a need for design and verification
engineers to work more closely together, and for designers to do some top-level
verification, often using formal or static techniques. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Q: Please
share your experiences with the evolution of verification?</span> </strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">At EE
Times, I wrote about many new verification companies and covered key product
announcements. At Cadence I was more focused on Cadence products, but I
continued to cover DVCon and other verification related</span><a href="https://www.blogger.com/null" name="_GoBack"></a><span style="font-family: Verdana, sans-serif;"> industry
events.<span style="mso-spacerun: yes;"> </span></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><span style="mso-spacerun: yes;"></span></span></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><span style="mso-spacerun: yes;"></span></span></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Q: Do you
believe that today verification accounts for 70% of the ASIC design cycle
efforts?</span> </strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">I
think we must be very careful with statements such as these. The <span style="color: white;">question is,
70% of what?</span> Are we looking at the entire ASIC/SoC design cycle, from software
development through physical design? Or are we considering just “front end”
hardware design? Are we talking about block-level verification or looking at
the whole SoC and the integration between IP blocks? The 70% claim is about
marketing, not engineering. </span></span></div>
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<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="color: #f1c232; font-family: Verdana, sans-serif;"><strong>Q: What
are the key technologies to look forward for in near future?</strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US"><span style="font-family: Verdana, sans-serif;">I think you’re going to see
software-driven verification methodologies that employ “use case” testing. The
idea here is to specify system-level verification scenarios that involve use
cases, and to automatically generate portable, constrained-random tests. The
tests are “software driven” because they can be applied through C code running
on embedded processor models. </span></span><span lang="EN-US"><span style="font-family: Verdana, sans-serif;">Another emerging concept is the “formal
app.” A formal app is an automated program that handles a specific task, such
as X state propagation. Today most providers of formal verification offer
formal apps.</span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Q: What
is that you would miss about our industry the most?</span> </strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">EDA is
a dynamic industry. There is always something new and exciting. I will miss the
constant innovation and the spirit that drives it. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Q: Words
of wisdom to the readers?</span> </strong></span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"><span style="font-family: Verdana, sans-serif;">Don’t
be afraid to try something new. Increasing chip and system complexity will
drive the need for more productive design and verification methodologies. Job
descriptions will change as software, hardware, analog, digital, and
verification engineers all need to work more closely together. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 10.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"><span style="font-family: Verdana, sans-serif;">Thank
you Richard for your answers. </span></span></div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"></span> </div>
<div class="MsoNoSpacing" style="margin: 0cm 0cm 0pt; text-align: justify;">
<span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"></span><span lang="EN-US" style="mso-bidi-font-size: 12.0pt;"><span style="font-family: Verdana, sans-serif;">Your
writings have helped in spreading the technology and inspired many of us to do
it ourselves too. Wish you happiness and good health!!! <o:p></o:p></span></span></div>
<div style="text-align: justify;">
</div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com1tag:blogger.com,1999:blog-9157206405178843096.post-39487190273086602942015-04-19T17:38:00.000+05:302015-04-20T15:59:27.723+05:30Moore's law - A journey of 50 years<div dir="ltr" style="text-align: left;" trbidi="on">
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">50 years of innovation! 50 years of quest with complexity! 50 years of Moore's law! Yes, April 19th is an important date for the semiconductor industry. It was on this date in 1965 that a paper was published citing Gordon Moore's observation - <em>the no. of transistors on a given silicon area would double in almost every two years</em>. The observation turned to be a benchmark and later a self fulfilling prophecy that is chanted by everyone whether an aspirant wanting to be a part of this industry or veteran who worked all throughout since the time when the law was still an observation! I myself remember my first interview as a fresh grad where I was asked the definition & implication of this law. It may not be a surprise if there is a survey done on one name that people in this industry have read, heard or uttered the most in their careers and the result would be MOORE unanimously!</span></div>
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</div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The below infographic from </span><a href="http://www.intel.com.tw/content/dam/staging/image/Kim/HTML%20Detail%20Pages/moores_Infographic_2-1.jpg"><span style="font-family: Verdana, sans-serif;">Intel </span></a><span style="font-family: Verdana, sans-serif;">would help you appreciate the complexity that we are talking about
–</span></div>
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<span style="font-family: Verdana, sans-serif;">
</span><br />
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<br />
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<span style="font-family: Verdana, sans-serif;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiNXV9pZu3P_zP09fncPDA2ay6zRLtKTj9JObIH9ivuyg_XozbkljbqcXiJx1kTaqep5xfvKk9XvQGQSlLUDtkEEgr5hK8Uqa9LkmqWOGxiUGf2rsL3s-7xjWvJ0hFL2PDcvLwUfRee4Tg/s1600/moores_Infographic_2-1.jpg" imageanchor="1" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiNXV9pZu3P_zP09fncPDA2ay6zRLtKTj9JObIH9ivuyg_XozbkljbqcXiJx1kTaqep5xfvKk9XvQGQSlLUDtkEEgr5hK8Uqa9LkmqWOGxiUGf2rsL3s-7xjWvJ0hFL2PDcvLwUfRee4Tg/s1600/moores_Infographic_2-1.jpg" height="320" width="640" /></a></span></div>
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<span style="font-family: Verdana, sans-serif;">In this pursuit to double the no. of transistors, there were major
shifts that the industry experienced. Let's have a look at the notable ones that had a major impact -</span></div>
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</div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Birth of EDA industry</span></strong> – As the numbers grew it was difficult
to handle the design process manually and there was a need for automating the
pieces. While the initial work in these lines happened in the design houses, it
was soon realized that re-inventing the wheel and maintaining proprietary flows
without considerable differentiation to end products wasn’t so very wise. This
lead to the birth of the design automation industry that today happens to be
the lifeline of the SoC design cycle.</span></div>
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</div>
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<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #ffe599;"><span style="color: #f1c232;">Birth of the fabless ecosystem</span> </span></strong>– The initial design houses
had the muscle to manufacture the end product while allowing some contract
manufacturing for the smaller players. This setup had its own set of issues discouraging startups. Also, maintaining the
existing node while investing in R&D for next gen nodes was
unsustainable. It was only in the late 80s when Morris Chang introduced the
foundry model that the industry realized fabless was a possibility. Since then,
all stakeholders of the ecosystem have collaborated towards realizing the Moore’s
law.</span></div>
<div style="text-align: justify;">
</div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Reuse</span></strong> – As the transistors scaled, the turnaround time to design
should have increased, but, to keep a check on the same, reusability was adopted.
This reuse was introduced at multiple levels. Different consortiums came
forward to standardize the design representations & hand offs. Standards
helped in promoting reuse across the industry. Next was design reuse in form of
IPs. For standard protocols the IPs are reused across companies while
for proprietary ones reuse within the organization is highly encouraged. Reuse
has played a significant role in continuing the pace that Moore’s law suggests.</span></div>
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<span style="font-family: Verdana, sans-serif;">
</span></div>
<div class="MsoNormal" style="margin: 0cm 0cm 10pt; text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Abstraction</span></strong> – When the observation was made, the design were
still at transistor level and layouts done manually. Due to the need to
sustain the rising complexity, it was realized to move to next level of
abstraction i.e. logic gates followed by Register Transfer level
where the design is represented in HDLs and synthesized to gates. Today the
industry is already talking about a still high level synthesizable language. </span></div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">
</span><span style="font-family: Verdana, sans-serif;"><strong><span style="color: #f1c232;">Specialization</span></strong> – The initial designs didn’t require a variety
of skill set as it is today. Given the evolution of the design cycle and the
quantum of responsibility at every stage, there was a need to bring in
specialists in each area. This lead to RTL designers, verification engineers, gate
level implementation engineers and layout engineers. Today the overall team
realizing a design runs into hundreds of engineers with varied skill set for a
complex SoC involving EDA, foundry, reuse & abstraction.</span></div>
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<span style="font-family: Verdana, sans-serif;">
</span></div>
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<span style="font-family: Verdana, sans-serif;">Throughout these 50 years, there were many a times when
experts challenged the sustainability of Moore’s law. Most of them had a scientific
rational endorsing their argument. However, the collective effort of the
industry always was able to find out an answer to those challenges – sometimes through
science, sometimes through logic and sometimes through sheer conviction!</span></div>
<div style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">
</span><span style="color: #e69138; font-family: Verdana, sans-serif;"><strong>Long live Moore’s law!</strong></span></div>
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<span style="font-family: Verdana, sans-serif;">
</span></div>
</div>
</div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com3tag:blogger.com,1999:blog-9157206405178843096.post-17730242302947656452015-03-22T14:52:00.002+05:302015-03-22T14:52:39.625+05:30Is Shift Left just a marketing gimmick?<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">This year <a href="http://www.dvcon.org/">DVCON</a> in US was a huge success hosting close to 1200+
visitors busy connecting, sharing & learning! With UVM adoption rate
stabilizing, this year the talk of the event was <b><span style="color: #f1c232;">‘Shift Left’</span></b> – a discussion
kicked off as a keynote by Aart J. De Geus, CEO of <a href="http://www.synopsys.com/home.aspx">Synopsys</a>. The reason for the generated interest is because
there are gurus preaching it to be the next big thing and then there are pundits
predicting it to be a mere marketing buzzword. In reality, both are correct! <o:p></o:p></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjBUrRl5cVG8qoc3YEm5pfrIoUIt-7Tm2Rhjw_1K6qgfIdrECEk7N-5tQRllfXEPEGQ7LglTH5PqRqAXfy7X08oGx-t11gJVOxxN5-1APffZ9Nm-RHftF5kWquBlk8gQiLgHKyOQ12fqoA/s1600/shiftleft.png" imageanchor="1" style="clear: left; display: inline !important; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjBUrRl5cVG8qoc3YEm5pfrIoUIt-7Tm2Rhjw_1K6qgfIdrECEk7N-5tQRllfXEPEGQ7LglTH5PqRqAXfy7X08oGx-t11gJVOxxN5-1APffZ9Nm-RHftF5kWquBlk8gQiLgHKyOQ12fqoA/s1600/shiftleft.png" /></a><span style="font-family: Verdana, sans-serif;">The term <span style="color: #f1c232;"><b>'Shift Left'</b></span> is considerably new and is interesting enough to create a buzz around the industry. Without the buzz there is no awareness and without awareness, no adoption! However, the phenomenon i.e. squeezing the development cycle aka <b><span style="color: #f1c232;">'Shift left'</span></b> for faster time to market has been there for more than a decade.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">In the 90s, hundreds of team members worked relentlessly to tape out 1 chip in years & were flown to destinations like Hawaii for celebrating it. Today this is no more heard because every organization or for that matter even the captive centres itself are taping out multiple chips per year. The celebration got squeezed to a lunch/dinner - probably indicating a <b><span style="color: #f1c232;">'Shift Left'</span></b> in celebrations too :)</span></div>
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<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Back in the 90s, the product was HE centric and the so called ASIC design cycle was fairly simple owing to its sequential nature where next stage starts once earlier is done. The industry saw this as an opportunity and started working towards tools & flows that can help bring in efficiency by parallelizing the efforts. Introduction to <a href="http://whatisverification.blogspot.in/2013/05/constrained-random-verification-flow.html">constrained random verification</a> lead the verification efforts to be parallel to RTL thereby stepping left. Early RTL releases to implementation team helped parallelizing the efforts towards floor planning, placement, die size estimation and package design etc. Reuse of IPs, VIPs, flow, methodologies etc gave further push enabling optimized design cycle. These efforts helped in bringing the first level of the now called <b><span style="color: #f1c232;">'Shift Left'</span></b> in the design cycle.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">In the later part of the last decade, 2 observations were evident to the industry -</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">1. The product is no longer HW alone and instead a
conglomeration of </span><a href="http://whatisverification.blogspot.in/2015/01/hw-sw-yes-steve-jobs-was-right.html" style="font-family: Verdana, sans-serif;">HW & SW</a><span style="font-family: Verdana, sans-serif;"> with the later adding further delays to the
overall product development cycle.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">2. Efficiency achieved out of parallelism is limited by the
longest pole of the divided tasks. In ASIC design cycle, <a href="http://whatisverification.blogspot.in/2012/04/verification-claims-70-of-chip-design.html">Verification happens to be gating</a> further squeeze in the cycle.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">This became the next focus area and today given that the
solutions have reached some level of maturity the buzz word that we call <b><span style="color: #f1c232;">‘Shift
Left’ </span></b>finally found an identity! The key ideas that enable this shift left
include –</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">- Formal APPS enabling faster targeted verification of
defined facets in any design. The static nature of the solution wrapped up in
form of APPS has tickled the interest in the design community to contribute to
verification productivity by cleaning up the design before mainstream
verification starts. This leads to another buzzword DFV - <span style="color: #f1c232;"><b>‘Design for
Verification’</b></span>.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">- FPGA prototyping has always been there but each
organization was spending time & efforts to define & develop the
prototyping board. Today off the shelf solutions give the desired jump start to the prototyping
process enabling early SW development once the RTL is mature.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">- To improve the speed of verification, hardware
accelerators aka emulation platforms were introduced and these solutions opened
up gates for early software development even before the RTL freeze milestone.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">- Improvement in speed with higher level of abstraction was
evident when the industry moved from Gate level to RTL. The next move was
planned with transaction level modelling. While high level synthesis is yet to
witness mass adoption, its extension resulted in Virtual prototyping platform
enabling architecture exploration, HW SW partitioning and early SW development
even before the RTL design/integration starts.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">In summary, the process of product development cycle is
getting refined by the day. The industry is busy weeding out inefficiencies in
the flow, automating everything possible to improve predictability and bringing
in the required collaboration across the stakeholders for realizing better,
faster & cheaper products. Yes, some call it the great </span><b style="font-family: Verdana, sans-serif;"><span style="color: #f1c232;">SHIFT LEFT</span></b><span style="font-family: Verdana, sans-serif;"><b><span style="color: #f1c232;">!</span></b></span></div>
</div>
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<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Today the traditional methods of verifying the design
strangle with complexity seeking new leaps and bounds. We discussed in our <a href="http://whatisverification.blogspot.in/2015/02/designers-should-not-verify-their-own.html">last post</a> about why a new
pair of eyes was added to the design flow and since then we continue to not
only increase the numbers of those pairs but also improve the lenses that these
eyes use to weed out bugs. These lenses are nothing but the flows and methodologies
we have been introducing as the design challenges continue to unfold. Today, we
have reached a point in verification where <span style="color: #f1c232;">‘one size doesn’t fit all’</span>. While
the nature of the design commands a customized process of verifying it, even
for a given design, moving from block to sub system (<a href="http://whatisverification.blogspot.in/2014/04/uvm-just-do-it-or-do-it-right.html">UVM centric</a>) and
to SoC/Top level (<a href="http://whatisverification.blogspot.in/2011/03/what-makes-optimal-soc-verification.html">directed tests</a>) we need to change the way we verify the
scope. Besides the level, there are certain categories of functions that are best
suited for a certain way of verification (read formal). Beyond this, modelling the
design and putting a reusable verification environment around it to accelerate
the development is another area that requires attention. With analog sitting next to
digital on the same die, verifying the two together demands a unique approach.
All in all, for the product to hit the market window in the right time you cannot
just verify the design but you need to put a well defined strategy to verify it
in the fastest and best possible fashion.</span></div>
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<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjlyPKZO_1faAszDL_y5PH7cM3xGfBh9tvSJ7wu5uVTQFJPqQjLIDmvjF5r7Mv_aJA0D95UIcc2erpV0CiM7Iu-SeqGJj7WjzeR1fxgWqfvzz-REndVT6T1WMHv1ympzH9pJJroW_diVuY/s1600/OODA.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjlyPKZO_1faAszDL_y5PH7cM3xGfBh9tvSJ7wu5uVTQFJPqQjLIDmvjF5r7Mv_aJA0D95UIcc2erpV0CiM7Iu-SeqGJj7WjzeR1fxgWqfvzz-REndVT6T1WMHv1ympzH9pJJroW_diVuY/s1600/OODA.png" height="272" width="320" /></a></div>
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<span style="font-family: Verdana, sans-serif;">So what is OODA loop? From <a href="http://en.wikipedia.org/wiki/OODA_loop">Wikipedia</a>, the phrase OODA
loop refers to the decision cycle of <b><span style="color: #f1c232;">observe,
orient, decide, and act</span></b>, developed by military strategist and USAF Colonel John Boyd. According to Boyd, decision making occurs in a recurring cycle of
<b><span style="color: #f1c232;">observe-orient-decide-act</span></b>. An entity (whether an individual or an organization)
that can process this cycle quickly, observing and reacting to unfolding events
more rapidly than an opponent, can thereby "get inside" the opponent's
decision cycle and gain the advantage. The primary application of OODA loop
was at the strategic level
in military operations. Since the concept is core to defining the right
strategy, the application base continues to increase. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">To some extent this OODA loop entered the DV cycle with the
introduction of <a href="http://whatisverification.blogspot.in/2013/05/constrained-random-verification-flow.html">Constrained Random Verification</a> paired with Coverage Driven
verification closure. Constrained random regressions kicked off the process of
observing the gaps, analyzing the holes, decide if they need to be covered and
acting on refining the constraints further so as to direct the simulations to
cover the holes. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Today, the need for applying OODA loop is at a much
higher level i.e. to strategize on the right mix of tools, flows and
methodologies in realizing a winning edge. The outcome depends highly on the 2 O’s
i.e. <b><span style="color: #f1c232;">Observe</span></b> <b><span style="color: #f1c232;">&</span></b> <b><span style="color: #f1c232;">Orient</span></b>. In order to maximize returns on these Os, one must
be AWARE of –</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">1. The current process that is followed </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">2 Pain points in the current process and anticipated ones for
the next design</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">3. Different means to address the pain points</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Even to address the first 2 points mentioned above, one
needs to be aware of what all to observe in the process and how to measure the
pain points. While the EDA partners try to help out in the best possible way
enabling the teams with the right mix, it is important to understand what kind
of challenges are keeping the the others in the industry busy and how are they solving these
problems. One of the premiere forums addressing this aspect is
<span style="color: #f1c232;"><b>DVCON!</b></span> Last year, DVCON extended its presence from US to <a href="http://whatisverification.blogspot.in/2014/07/dvcon-goes-global.html">India and Europe</a>. These events provide a unique opportunity to get involved and in the process - connect, share and learn. </span><span style="font-family: Verdana, sans-serif;">Re-iterating the words of Benjamin Franklin once again
–</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: center;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><i>Tell me and I forget.</i></span></div>
<div class="MsoNormal" style="text-align: center;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><i>Teach me and I remember.</i></span></div>
<div class="MsoNormal" style="text-align: center;">
<span style="color: #f1c232; font-family: Verdana, sans-serif;"><i>Involve me and I learn.</i></span></div>
<div class="MsoNormal" style="text-align: center;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;">So this is your chance to contribute to enabling the fraternity
with the Os of OODA loop!</span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;"><span style="color: #f1c232;">Relevant dates -</span></span></div>
<div class="MsoNormal" style="text-align: left;">
<a href="http://dvcon.org/" style="font-family: Verdana, sans-serif; text-align: justify;">DVCON US</a><span style="font-family: Verdana, sans-serif; text-align: justify;"> </span><span style="font-family: Verdana, sans-serif; text-align: justify;">– March 2-5, San Jose</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><a href="http://dvcon-india.org/">DVCON India</a> – September 10-11, Bangalore</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><a href="http://dvcon-europe.org/">DVCON Europe</a> – November 11-12, Munich</span></div>
<div>
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;"><span style="color: #f1c232;">Other posts on DVCON at siddha'karana –</span></span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;"><a href="http://whatisverification.blogspot.in/2014/07/dvcon-goes-global.html">DVCON goes GLOBAL!</a></span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;"><a href="http://whatisverification.blogspot.in/2014/09/dvcon-india-journey-of-verification.html">DVCON India : Journey of Verification (preview)</a></span></div>
<div class="MsoNormal" style="text-align: left;">
<span style="font-family: Verdana, sans-serif;"><a href="http://whatisverification.blogspot.in/2014/10/dvcon-india-2014-event-recap.html">DVCON India 2014 : Event Recap!</a></span></div>
<br />
<div class="MsoNormal" style="text-align: left;">
<br /></div>
</div>
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<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com0tag:blogger.com,1999:blog-9157206405178843096.post-90595702924348051202015-02-08T16:50:00.000+05:302015-02-08T16:50:03.276+05:30Designers should not verify their own code! REALLY?<div dir="ltr" style="text-align: left;" trbidi="on">
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Around 2 decades back, the demands from designs were relatively simple and the focus was on improving performance. Process nodes had longer
life, power optimization wasn’t even discussed and time to market pressure was
relatively less given that the end products enjoyed long life. In those days,
it was the designer who would first design and later verify his own code
usually using the same HDL. Over the years, as complexity accelerated, a new breed of engineers entered the scene, the DV engineers! The rational
given was that there is a <b><span style="color: #f1c232;">need for an independent pair of eyes to confirm if the design is
meeting the intent!</span></b> Verification was still sequential to the design in early days of directed verification. Soon, there was a need for constrained random verification
(<a href="http://whatisverification.blogspot.in/2013/05/constrained-random-verification-flow.html">CRV</a>) and additional techniques to contain the growing verification challenge. The
test bench development now started in parallel to the design, improving the size & need of verification teams further. With non HDLs i.e. HVLs entering the
scene the need for DV engineers was inevitable. All these years, the rational
of having an additional pair of eyes continued to be heard to an extent that we
have started believing that designers should not verify their own code. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">In my <a href="http://whatisverification.blogspot.in/2015/01/the-4th-c-in-verification.html">last post</a> I emphasized the need for collaboration
wherein designers and verification engineers need to come together for faster
verification closure. Neil Johnson recently concluded in his <a href="https://www.linkedin.com/pulse/thou-shalt-verify-your-own-code-neil-johnson">post</a> on designers
verifying their own code. My 2 cents to whether
designers <b><span style="color: #f1c232;">should not</span></b> or shall I say <b><span style="color: #f1c232;">do not</span></b> verify their own code –</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhInhihb-TGiXpSh8QMRe9HtzD2OkLguR2FPAOEycYJgQ1slzhUOVKlYA9tkj79mm1CWZR_495kd7gviHVy1lM0N8ja4s0ia61IhAvQiyu0f1kY637hlvGrwk3u3KXXiaat3Fe3WsKCUgU/s1600/effort.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhInhihb-TGiXpSh8QMRe9HtzD2OkLguR2FPAOEycYJgQ1slzhUOVKlYA9tkj79mm1CWZR_495kd7gviHVy1lM0N8ja4s0ia61IhAvQiyu0f1kY637hlvGrwk3u3KXXiaat3Fe3WsKCUgU/s1600/effort.png" height="236" width="320" /></a></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">To start with, let’s look at what all involves verification? The
figure adjoining is a summary of efforts spent in verification based on the study conducted by <a href="http://blogs.mentor.com/verificationhorizons/blog/2013/07/22/part-6-the-2012-wilson-research-group-functional-verification-study/">Wilson research in 2012</a>
(commissioned by Mentor). </span><span style="font-family: Verdana, sans-serif; text-align: left;">Clubbing some of the activities it is clear that ~40% of
the time is spent in Test planning, Test bench development and other
activities. The rest ~60% of the effort is spent on Debug & creating + running
tests. The DUT here can be an IP or SoC. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">When an IP is under development or SoC is getting integrated,
the DV engineers would be involved into the 40% of the activities mentioned
above. These are the tasks that actually fall in line with the statement of <span style="color: #f1c232;"><b>additional
pair of eyes validating design intent</b></span>. They need to understand the
architecture of the DUT and come up with a verification plan, develop
verification environment and hooks to monitor progress. At this level, the
involvement of the design team starts with activities like test plan review,
code coverage review, inputs to corner cases and tests of interest. </span></div>
<div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">So, once the
design is alive on the testbench, do the designers just sit & watch the DV
team validate the representation of spec developed by them? <b>NO! </b></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Debugging alone is a single major activity that consumes an
equal amount or sometimes more efforts from the designers to root cause the
bug. Apart from it, there is significant involvement of the design team during
IP & SoC verification.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">For IPs, CRV is a usual choice. The power of CRV lies in automating
the test generation using the testbench. A little additional
automation enables the designers to generate constrained tests themselves. Assertions
are another very important aspect in IPs. With introduction of assertion
synthesis tools, the designers work on segregating the generated points into
assertions or coverage. </span><span style="font-family: Verdana, sans-serif;">For SoCs, apart from reuse of CRV, directed verification is
an obvious choice. Introduction to new tools on graph based verification help designers
to try out tests based on the test plan developed by the DV engineer. Apart
from this, corner case analysis and usecase waveform reviews are another time
consuming contributions put in by designers for verifying the DUT.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Coming back to the rational on <b><span style="color: #f1c232;">having an independent pair of
eyes verify the code</span></b>, the implication was never that the designers shall not verify
their own code. Infact there is no way for the DV team to do it in a disjoint
fashion. </span><span style="font-family: Verdana, sans-serif;">Today the verification engineer himself is designing a highly
sophisticated test bench that is actually equivalent to a designer’s code in complexity.
So it would be rather apt to say that it is the
two designs striking each other to enable verification under the collaboration
between design & verification teams!</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">What is your take on this? Drop a note below!</span></div>
</div>
</div>
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<div style="text-align: left;">
</div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<div class="separator" style="clear: both; text-align: center;">
</div>
<div class="separator" style="clear: both; text-align: center;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiKQwSte2s9Piaw8NjN9I70CNX9Xu-DeLvJOr55gUROOXjGDSYc1_Y68Js01rbHOZ4riOMjL2yhYImrHgTac9szFqjd_PgwCtQoMBGkTxMR5Xs8Mv2218lwQg9S9Z6K2BufegryCzTDXZA/s1600/INSTITUI%C3%87%C3%95ES-SOCIAIS-EM-SOCIOLOGIA.jpg" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiKQwSte2s9Piaw8NjN9I70CNX9Xu-DeLvJOr55gUROOXjGDSYc1_Y68Js01rbHOZ4riOMjL2yhYImrHgTac9szFqjd_PgwCtQoMBGkTxMR5Xs8Mv2218lwQg9S9Z6K2BufegryCzTDXZA/s1600/INSTITUI%C3%87%C3%95ES-SOCIAIS-EM-SOCIOLOGIA.jpg" /></a></div>
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<span style="font-family: Verdana, sans-serif;">The 3C’s of verification i.e. Constraints, Checkers &
Coverage have been playing an important role enabling faster verification
closure. With growing
complexity and shrinking market windows it is important to introduce the 4<sup>th</sup>
C that can be a game changer in actually differentiating your product
development life cycle. Interestingly the 4<sup>th</sup> C is less technical
but highly effective in results. It is agnostic to the tool or flow or
methodology but if introduced and practiced diligently
would surely result in multi-fold returns. Since <a href="http://whatisverification.blogspot.in/2012/04/verification-claims-70-of-chip-design.html">verification claims almost 70%of the ASIC design cycle</a>, it is evident that timely sign off on DV would be the
key to faster time to market of the product. Yes, the 4<sup>th</sup> C I am referring to is <b><span style="color: #f1c232;">Collaboration</span></b>!</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><a href="http://whatisverification.blogspot.in/2011/03/uvm-redefining-verification-play-field.html">UVM</a> demonstrates a perfect example of collaboration within
the verification fraternity to converge on a methodology that benefits
everyone. Verification today spreads beyond RTL simulations to high level model
validation, virtual platform based design validation, analog model validation, static
checks, timing simulations, FPGA prototyping/emulation and post silicon
validation. What this means is that we need to step out and collaborate with
different stakeholders enabling faster closure.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The first & foremost being the architecture team, RTL
designers & analog designers who conceive the design and realize it in some
or the other form and many a times fall short of accurate documentation. The architecture
team can help to a large extent in defining the <a href="http://whatisverification.blogspot.in/2014/10/moving-towards-context-aware.html">context under which theverification</a> needs to be carried out thereby narrowing down the scope. With a
variety of tools available, the DV teams can work closely with designers to clean
the RTL removing obvious issues that otherwise would stall simulation progress.
Further, assertion synthesis and coverage closure would help in closing
the verification at different levels smoothly. Working with analog designers
can help tune the models and their validation process wrt the circuit
representation of the design. This enables faster closure of designs that see
increased scope of analog on silicon.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Next are the tools that we use. It is important to
collaborate with the EDA vendors in not just being the user of the tool but
working closely with them in anticipating the challenges expected in the next
design and be early adopters of the tools to flush the flows and get ready for
the real drill. Similarly, joining hands with the IP & VIP vendors is equally
crucial. Setting up right expectations with the IP vendors on the deliverables from
verification view point i.e. coverage metrics, test plans, integration guide,
integration tests etc. would help in faster closure on SoC verification. Working
with VIP vendors to define how best to leverage the VIP components, sequences,
tests & coverage etc. at block and SoC level avoids redundant efforts and
help in closing verification faster. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">The design service providers augment the existing teams
bringing the required elasticity to the project needs or take up ownership of
derivatives and execute them. These engineers are exposed to a variety of flows
and methodologies while contributing to different projects. They can help in
introducing efficiency to the existing ways of accomplishing tasks. Auditing
existing flows and porting the legacy environment to better ones is another way
these groups can contribute effectively if partnered aptly. </span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Finally the software teams that bring life to the HW we
verify. In my last <a href="http://whatisverification.blogspot.in/2015/01/hw-sw-yes-steve-jobs-was-right.html">blog</a> I highlighted the need for HW & SW teams to work
more closely and how verification teams acts as a bridge between the two. Working
closely with the SW teams can improve reusability and eliminate redundancies in
the efforts.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<br />
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><span style="color: #f1c232;">Collaboration today is the need of the hour</span>! We need to be
open to recognize the efforts put in by different stakeholders from the
ecosystem to realize a product. Collaboration improves reuse and avoids a lot
of wasted efforts in terms of repeated work or incorrect understanding of
intent. Above all, the camaraderie developed as part of this process would
ensure that any or all these folks are available at any time to jump in the
hour of need to cover for unforeseen effects of Murphy’s law.</span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;"><br /></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-family: Verdana, sans-serif;">Drop in your experiences & views with collaboration in the comments section.</span></div>
</div>
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<div style="text-align: justify;">
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<div class="MsoNormal" style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">The start of the year marked another step forward towards
the NEXT BIG THING in semiconductor space with a fleet of companies showcasing
interesting products at <a href="http://www.cesweb.org/News/CES-Social">CES</a> in Las Vegas. In parallel, the <a href="http://vlsidesignconference.org/">VLSI conference 2015</a>
at Bangalore also focused on <span style="color: #f1c232;"><b>Internet of Things</b></span> with industry luminaries
sharing their views and many local start-ups busy demonstrating their products.
As we march forward to enable everything around us with sensors, integrating connectivity through gateways and associated analytics in the cloud, the
need for lower form factors, low power, efficient performance and high security
at lowest possible cost in limited time is felt more than ever. While there has
been a remarkable progress in SoC development targeting these goals, the end
product landing with the users doesn’t always reflect the perceived outcome. What
this means is, we are at a point where HW and SW cannot work in silos anymore
and they need multiple degrees of collaborations.</span></span></div>
<div class="MsoNormal">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglRYHCI68bH5V_EkgbTqzRWXmJDhjKvsiLUFh27F-3hVy3A-Chi8p3V6cc2YqFlVm19vOoRG0KapKPlDIiLreGSqqqphCvt4xkxKIyatRgJgd36Hi9I2ZCmRsSEzNH254m0epjpkKZYss/s1600/Steve-Jobs-quote-2-sep.png" imageanchor="1" style="clear: left; float: left; margin-bottom: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglRYHCI68bH5V_EkgbTqzRWXmJDhjKvsiLUFh27F-3hVy3A-Chi8p3V6cc2YqFlVm19vOoRG0KapKPlDIiLreGSqqqphCvt4xkxKIyatRgJgd36Hi9I2ZCmRsSEzNH254m0epjpkKZYss/s1600/Steve-Jobs-quote-2-sep.png" height="239" width="320" /></a><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">To enable this next
generation product suites, there is a lot of debate going around the CLOSED
& OPEN source development. Every discussion refers to the stories of Apple
vs Microsoft/Google or iOS vs Android etc. While an open source definitely accelerates
development in different dimensions, we all would agree that some of the major
user experiences were delivered in a closed system. Interestingly, this debate
is more philosophical! At a fundamental level, the reason for closed development was to
ensure the HW and SW teams are tightly bound – a doctrine strongly preached by
Steve Jobs. From an engineering standpoint, with limited infrastructure
available around that time, a closed approach was an outcome of this
thought process. Today, the times have changed and there are multiple options
available at different abstraction levels to enable close knitting of HW and SW. </span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">To start with, the basic architecture exploration phase of
partitioning the HW and SW can be enabled with the virtual platforms. With the
availability of high level models one can quickly build up a desired system to
analyze the bottlenecks and performance parameters. There is work in progress
to bring power modelling at this level for early power estimation. A transition
to cycle accurate models on this platform further enables early software
development in parallel to the SoC design cycle. </span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Once the RTL is ready, the emulation platforms accelerate
the verification cycle by facilitating the testing to be carried out with the external
devices imitating real peripherals. This platform also enables the SW teams to
try out the code with the actual RTL that would go onto the silicon. The
emulators support performance and power analysis that further aid in ensuring
that the target specification for the end product is achieved. </span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Next, the advancements in FPGA prototyping space finally gives
the required boost to have the entire design run faster ensuring
that the complete OS can be booted with use-cases running much ahead of the Si tape-out
providing insurance to the end product realization.</span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<br /></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">This new generation of EDA solutions are enabling the bare
metal software development to work in complete conjunction with the hardware
thereby exploiting every single aspect of the later. It is the verification team
that is morphing itself into a bridge between the HW and SW team enabling
the <a href="http://whatisverification.blogspot.in/2014/06/shift-left-and-reuse-in-verification.html">SHIFT LEFT</a> in the product development cycle. While the industry pundits can
continue to debate over the closed vs open philosophy, the stage is all set to
enable HW SW co-development in a given proximity under either of these cases.</span></span></div>
<div class="MsoNormal" style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><br /></span></span></div>
<div style="text-align: justify;">
<span style="font-size: small;"><span style="font-family: Verdana,sans-serif;"><span style="line-height: 115%;">As Steve Jobs believed, the differentiation
between a GOOD vs GREAT product is the tight coupling of the underlying HW with
the associated SW topped with simplicity of use. Yes, Steve Jobs was right and today we see technology enabling his vision for everyone!</span></span></span></div>
<div style="text-align: justify;">
<br /></div>
<div class="MsoNormal">
<span style="color: #e69138;"><span style="font-size: small;"><span style="font-family: Verdana,sans-serif;">Wish you & your loved ones a Happy and Prosperous 2015!</span></span></span></div>
<div class="MsoNormal">
<br />
<span style="font-size: x-small;"><span style="font-family: Verdana,sans-serif;"><i>Disclaimer: The thoughts shared are an individual opinion of the author and not influenced by any corporate.</i></span></span></div>
<div style="text-align: justify;">
<br /></div>
</div>
<div class="blogger-post-footer"><a href="https://twitter.com/share" class="twitter-share-button" data-via="gjalan">Tweet</a>
<script>!function(d,s,id){var js,fjs=d.getElementsByTagName(s)[0];if(!d.getElementById(id)){js=d.createElement(s);js.id=id;js.src="//platform.twitter.com/widgets.js";fjs.parentNode.insertBefore(js,fjs);}}(document,"script","twitter-wjs");</script></div>Gaurav Jalanhttp://www.blogger.com/profile/16509909311582718412noreply@blogger.com0tag:blogger.com,1999:blog-9157206405178843096.post-525678644002546672014-12-28T19:46:00.001+05:302014-12-28T21:18:49.382+05:30Top 10 DV events of 2014<div dir="ltr" style="text-align: left;" trbidi="on">
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<table cellpadding="0" cellspacing="0" class="tr-caption-container" style="float: left; margin-right: 1em; text-align: left;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjDp7EbSyERRaGTn89f8LKN69UO-FqRVwq-PUsAD4yWBkLZIGh9ObDJZzgLQTOhvGdqu-EOecJxacmM2-Gm4aD1-P8SwyYNQ7j7PsHEQZfsjq0FgmK76YQrANst_-U2sMsZUI8MQgk10g0/s1600/crop380w_top-ten-articles-of-2014.jpg" imageanchor="1" style="clear: left; margin-bottom: 1em; margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjDp7EbSyERRaGTn89f8LKN69UO-FqRVwq-PUsAD4yWBkLZIGh9ObDJZzgLQTOhvGdqu-EOecJxacmM2-Gm4aD1-P8SwyYNQ7j7PsHEQZfsjq0FgmK76YQrANst_-U2sMsZUI8MQgk10g0/s1600/crop380w_top-ten-articles-of-2014.jpg" height="131" width="200" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;"><span style="font-size: xx-small;"><span style="font-family: Verdana,sans-serif;">www.fastweb.com</span></span></td></tr>
</tbody></table>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">The semiconductor industry while growing at a modest rate
is at crossroads to define the next killer category of products. The
growth in the phone and tablet segment is bound to follow the footsteps of PC
industry. IoT (Internet of Things) has been the buzzword but clear definition
of the road map is still fuzzy. Infrastructure as always would continue to grow
due to the insatiable appetite for faster connectivity and explosion in the
amount of data coming in with cloud computing. Irrespective of the product
definitions the need for increased functionality on smaller die size with low
power and faster time to market at low cost would prevail. To respond to this
demand, the DV community has been gearing up in small steps and some of those
important ones were taken in 2014. As the stage is getting ready to bid
farewell to 2014 and welcome the New Year, let’s have a quick recap of these
events in no particular order –</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">1. <span style="color: #f1c232;"><b>UVM 1.2</b></span> - A <a href="http://whatisverification.blogspot.in/2014/04/uvm-just-do-it-or-do-it-right.html">final version</a> of Universal Verification
Methodology, was released by Accellera for public review before taking it
forward for IEEE standardization. This finally marks an end to the methodology
war and resulting confusion. </span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">2. <span style="color: #f1c232;"><b>PSPWG</b></span> – While UVM has been an anchor for IP verification
and reuse, verification of complex scenarios at SoC level is still a challenge
particularly when multiple processors are involved and we are looking for reuse
across compute platforms. Portable Stimulus Proposed Working Group kicked off
this year bringing in stakeholders across the industry to brainstorm on a
Unified Portable Stimulus definition as a potential answer to the SoC
verification challenge.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">3. <span style="color: #f1c232;"><b>Formal</b></span> – Cadence buys Jasper for $170m claiming the
largest formal R&D team on the planet. It is expected to help
the customers further wherein integration of best of formal technologies from
either side would combine and complement the simulation and emulation
platforms. </span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">4. <span style="color: #f1c232;"><b>Verification Cockpit</b></span> – Another interesting shift seen
with major EDA vendors is pulling all verification solutions
under one umbrella. This includes simulation, emulation, prototyping, formal,
coverage, debug and VIPs etc. This is an important step for future SoCs wherein
the DV engineer can use the best solution for a given problem to achieve faster
verification sign-off.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">5. <span style="color: #f1c232;"><b>Emulation</b></span> – The wait was finally over where emulation
solutions found wide adoption across the industry. This year witnessed that
emulation is no more a luxury but a necessity to meet product schedule by accelerating
verification turnaround and enabling the <a href="http://whatisverification.blogspot.in/2014/06/shift-left-and-reuse-in-verification.html">shift left</a> in the product development
cycle. <span style="mso-spacerun: yes;"> </span></span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">6. <span style="color: #f1c232;"><b>DVCON</b></span> – This year marked another milestone where in DVCON
expanded its reach with Accellera sponsoring <a href="http://whatisverification.blogspot.in/2014/10/dvcon-india-2014-event-recap.html">DVCON India</a> and <a href="http://whatisverification.blogspot.in/2014/07/dvcon-goes-global.html">DVCON Europe</a>
providing an excellent platform for engineers to connect and share their
experiments and experiences.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">7. <span style="color: #f1c232;"><b>AMS</b></span> – Mentor Graphics acquired Berkeley Design
Automation, Inc., bringing in the required flow addressing analog,
mixed-signal, and RF circuit verification. This move is a step to integrate
a fairly focused solution with the existing expertise at Mentor to address the
next generation verification challenges that would unfold as analog claims more
% on silicon. </span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">8. <span style="color: #f1c232;"><b>VIP</b></span> – This year going with VIP solutions was a no
brainer. The pitch of buy vs sell is long gone and industry has embraced third
party VIPs with open arms. For a change, non occurrence of any major event in
VIP domain was itself an event!</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">9. <span style="color: #f1c232;"><b>X prop</b></span> – Another solution in verification that created
much steam is the X-prop solution from all vendors to enable weeding out the
functional X-s from the design at RTL level. This helped many projects reduce
the turnaround time spent with GLS.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">10. <span style="color: #f1c232;"><b>Standards</b></span> </span><span style="font-family: Verdana,sans-serif;"><span style="font-family: Verdana,sans-serif;">–</span> Accellera announced revision of few other standards that
include SystemC core language (<b>SystemC 2.3.1</b>) an update to the standard
released in 2011 focusing on transaction level modelling, SystemC verification
library (<b>SCV 2.0</b>) containing implementation of the verification extensions and
<b>Verilog-AMS 2.4</b> that includes extensions to benefit verification, behavioral modelling
and compact modelling.</span></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="font-family: Verdana,sans-serif;">I hope you had an eventful 2014 with different tools,
flows and methodologies. Drop in a comment with what you felt was most interesting in
2014 as we welcome 2015 and the events that would unfold with time. </span></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
<br /></div>
<div class="MsoNoSpacing" style="text-align: justify;">
<span style="color: #e69138;"><b><span style="font-family: Verdana,sans-serif;">Wish you all a Happy and Eventful 2015!</span></b></span></div>
<div style="text-align: justify;">
</div>
<div class="MsoNoSpacing" style="text-align: justify;">
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