Sunday, April 17, 2011

Verification Trends

DVCON 2011, held at San Jose between FEB 28th to MAR 3rd was quite a success. While UVM dominated the conference, the keynote from Walden C. Rhines, CEO Mentor Graphics was quite very interesting. The presentation, “From Volume to Velocity” touched upon the what’s going on in verification for past few years and challenges for future. Some of the interesting facts highlighted in the presentation were an outcome of one of the largest functional verification studies carried out by Wilson Research Group in 2010, commissioned by Mentor Graphics. Harry Foster has been writing a series of blogs summarizing this study.

The study distributes info in following regions –
- North America       : Canada, United States
- Europe/Israel        : Finland, France, Germany, Israel, Italy, Sweden, UK
- Asia (minus India) : China, Korea, Japan, Taiwan
- India

Here are a few interesting items  picked from the presentation and the blog . The comparisons are in reference to the 2007 Far West Research study.

DESIGN vs VERIFICATION in last 3 years

New logic development reduced by 34% and External IP adoption increased by 69%.
New verification code reduced by 24% and External VIP adoption increased by 138%.
Design teams have grown by 3.8% only.
Verification teams have grown by 58.34%.
Mean time a designer spends on verification has increased from 46% to 50%.

Trends -
- SOC designs are the key to suffice the appetite of next gen electronic products.
- 'Need to Standardize' is directly proportional to 'Need to Reuse'.
- Challenges in verification increase multifold with increase in design complexity.
- Jobs in verification continue to rise in comparison to other ASIC skills.
- Considering the demand, VIP business is luring. The business models for VIP (license based mostly) vs IP (royalty based mostly) makes it even more appealing.
 
FACTS about VERIFICATION

~66% projects are still not on schedule with functional bugs causing 50+% respins.
Mean time a verification engineer spends on various activities include –
   o 32% Debugging
   28% test bench development
   27% writing and debugging tests
   ~14% Others
Median number of verification engineers engaging on related activities –
   o Formal analysis – 1.68 in 2007 à 1.84 in 2010
   o FPGA prototyping – 1.42 in 2007 à  2.04 in 2010
   o HW acceleration/Emulation  – 1.31 in 2007 à 1.86 in 2010

Trends –

- Random verification adding volume is stagnating to meet verification challenges for next level mainly due to limitation on hardware resources and debugging time.
- Random verification is still not the preferred approach at SOC level.
- HW assisted acceleration needs to evolve further to ease random verification debug.
- Mention to Cloud computing was missing in the study as it is still evolving. However that should find a breather for hardware resource constraint in random simulations.
- Adoption of Formal verification should modulate the time spent on various verification activities.

- Advancements in verification have been reactive and unable to control the functional failure rate as complexity increases.

Geographical TRENDS in VERIFICATION
Based on the adoption rate the data is restructured below to highlight the #1 & #2.
ITEM
North America
Europe
Asia - India
India
Methodology  adoption
Code coverage
2
1
Functional coverage
2
1
Assertions
1
2
Emulation
2
1
FPGA prototyping
1
2
HVL adoption
System Verilog
1
2
Specman E
1
2
Vera
2
1
System C
2
1
BCL methodology adoption
UVM
1
2
OVM
2
1
VMM
1
2
eRM
1
2
AVM
2
1
RVM
1
2
Trends -
- India is among top 2 in 10/15 items. Infact it is marginally lagging in rest 4. This reflects the diverse skill set developed by India particularly in verification. FPGA prototyping is one area where it is last.
- Since functional coverage is not utilized a lot at SOC level as it is done at IP level, the data would make more sense if it includes IP verification vs SOC verification categories for the above items.
- Adoption of SystemC as an HVL is debatable as it is touted as a modeling language. Infact with ESL gaining momentum it would be interesting to see the dynamics between SystemC and System Verilog adoption.
- Specman-E adoption though small, enjoys a strong base. If UVM adds multi-language support, it will stabilize the ‘e’ adoption further.
Finally, the key to see convergence on verification as rightly pointed out by Wally Rhines is -  “Shift from Increasing Cycles of verification to maximizing verification per cycle” both from the EDA tools and the verification engineers.

NOTE - The data referenced from the study remains the sole property of Mentor Graphics.

7 comments:

  1. Linkedin Group: Professional Verification Experts

    Software, software, software... thats a real trend in hardware verification, at least if we look into system and SoC verification. It might not be the case for isolated IP, but everything above that includes software today. The old way of verifying a SoC without having the software integrated does not reflect an up to date verification strategy. This is true for functional simulation based verification as well as for formal verification.

    Posted by Markus Winterholer

    ReplyDelete
  2. Linkedin Group: Professional Verification Experts

    Even isolated IPs are also being verified using HVLs like SystemVerilog,Vera,Specaman, and all these contains tremendous amount of OOPs(software) concepts like class inheritance,polymorphisms,callbacks etc..

    Posted by Ram Narayan

    ReplyDelete
  3. Linkedin Group: Professional Verification Experts

    Verification has moved beyond just. "Register access or connectivi
    ty check'. Without full system level knowledge or in simple words use case validation is must to sign off any SoC.

    Niyaz Mulla

    ReplyDelete
  4. LinkedIn Groups : Design Verification Professionals

    Great Article.....
    Thanks

    Posted by Lopamudra Sen

    ReplyDelete
  5. Hi,

    First, thanks for this great article.

    I am a verification engineer and looking for new verification ways.
    In your article you talk about formal verification "Adoption of Formal verification should modulate the time spent on various verification activities", but I don't understand how it can. Could you please explain how it can help?

    One more question: Do you have any recommendation for gate level running. Actually I spend a lot of time in gate level running, and I ask myself whether it is necessary to run all the regression in gate level or only a part of my tests bucket? Maybe there is another way to check the design at gate level?

    Again Thanks for all your comment I really appreciate.

    Best Regards,
    Paul.

    ReplyDelete
  6. Came across this - what ya'll think? http://www.thevtool.com/

    Basically a GUI assisting in the verification process, much like a wordpress or wix might simplify the web design/development process.

    ReplyDelete
  7. The website seems to indicate information but not much in detail. It would be good if they can put up a demo video to showcase an example. Alternately, I am open to look into the tool & provide feedback if they can share some more insights.

    ReplyDelete