Thursday, December 30, 2010

2010 : Bidding Adieu

2010 has been an eventful year on all fronts for everyone.
After experiencing a worse downturn, the semiconductor industry witnessed close to +30% YoY growth in 2010. Customers, revenues, profits and jobs kept adding up month after month.

The verification space saw a lot of activity on multiple fronts.
A few highlights include -

- IEEE 1800-2009, a revision to existing System verilog standard was completed.
- UVM : Early Adopter version was released.
- Enhancements made to UPF IEEE standard.
- A lot of other (coverage, IP, AMS) standardization efforts progressed.
- ESL picked up after much delay.
- Formal verification complemented simulations more than ever.
- FPGA verification came up as hot topic.

- sid'dha-karana, a blog focused on verification kicked off.

On a closing note for the year, a few personal recommendations from 2010 -


Evolution of design methodology - Part I

Evolution of design methodology - Part II


Sand to silicon : the making of a chip

At this juncture I would like to thank you for your valuable feedback, support  and readership. I look forward for the same in 2011.

Wish you and your family "HAPPY & PROSPEROUS 2011".


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