To pursue a career in engineering, all of us have been through multiple courses in mathematics. All these courses involved proving equations or theorems. Given a relationship between variables we are asked to prove that relationship. There are defined methods and by following a step by step approach we are able to derive the desired proof. All this time we focus on proving LHS == RHS. Now imagine, if you are asked to prove the equivalence (LHS == RHS) by proving that there can be no way (LHS != RHS) the equation is non equivalent.
Sounds like a bully?
Interestingly, the whole practice of verifying semiconductor designs is based on this puzzling statement.
'Verification' i.e. sid'dha-karana, is a noun to the verb 'verify derived from Medieval Latin verificare : verus = true + facere = to make. So the literal meaning of the verification engineer's job is to make it true.
In an ideal world a fully verified design is the one where we have a PROOF of NO BUG (PNB) in the design. But the first learning imbibed in a verification engineer is that we cannot achieve 100% verification - an unconscious setback on the way one has been proving equality. A number of limitations (engineering or hardware resources, tools, schedule to name a few) that laid the foundation of this unachievable 100% verification has tossed the regular equation and shifted our focus from PNB to NPB i.e. NO PROOF of BUG. The verification engineer thus endeavors to pursue all means to make sure there is no proof of a bug found (feels like a daunting task if you still relate it with proving there is no way that the equation is non equivalent). With a set of tools, methodologies, languages and checklists the hunt for the bugs i.e. all possible ways to prove the non equivalence begins. Slowly, as we approach closer to verification closure, the constantly passing regression and diminishing bug rate strengthens our assumption that no more bugs are concealed. With verification sign off, the design is labeled BUG FREE with the assumption that hopefully if no more bugs discovered, NPB == PNB. Silicon validation adds more credibility to our assumption, while the team lives with anxiety during the Si bring up. If we are fortunate enough to have customers who explored the design in the way we did in verification the assumption becomes immortal…. Happy ending!
Of course if we miss one of the way(s) of reaching to the bug(s), the result is much more costly in cash & kind when compared to our inability in proving an equation before our Maths teacher.
Maybe that’s the risk we as verification engineers assume when we pick NPB over PNB for whatever reasons.
Happy BUG hunting! :)
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