The 4th C in Verification

The 3C’s of verification i.e. Constraints, Checkers & Coverage have been playing an important role enabling faster verification closure. With growing complexity and shrinking market windows it is important to introduce the 4^th C that can be a game changer in actually differentiating your product development life cycle. Interestingly the 4^th C is less technical but highly effective in results. It is agnostic to the tool or flow or methodology but if introduced and practiced diligently would surely result in multi-fold returns. Since verification claims almost 70%of the ASIC design cycle, it is evident that timely sign off on DV would be the key to faster time to market of the product. Yes, the 4^th C I am referring to is Collaboration!

UVM demonstrates a perfect example of collaboration within the verification fraternity to converge on a methodology that benefits everyone. Verification today spreads beyond RTL simulations to high level model validation, virtual platform based design validation, analog model validation, static checks, timing simulations, FPGA prototyping/emulation and post silicon validation. What this means is that we need to step out and collaborate with different stakeholders enabling faster closure.

The first & foremost being the architecture team, RTL designers & analog designers who conceive the design and realize it in some or the other form and many a times fall short of accurate documentation. The architecture team can help to a large extent in defining the context under which theverification needs to be carried out thereby narrowing down the scope. With a variety of tools available, the DV teams can work closely with designers to clean the RTL removing obvious issues that otherwise would stall simulation progress. Further, assertion synthesis and coverage closure would help in closing the verification at different levels smoothly. Working with analog designers can help tune the models and their validation process wrt the circuit representation of the design. This enables faster closure of designs that see increased scope of analog on silicon.

Next are the tools that we use. It is important to collaborate with the EDA vendors in not just being the user of the tool but working closely with them in anticipating the challenges expected in the next design and be early adopters of the tools to flush the flows and get ready for the real drill. Similarly, joining hands with the IP & VIP vendors is equally crucial. Setting up right expectations with the IP vendors on the deliverables from verification view point i.e. coverage metrics, test plans, integration guide, integration tests etc. would help in faster closure on SoC verification. Working with VIP vendors to define how best to leverage the VIP components, sequences, tests & coverage etc. at block and SoC level avoids redundant efforts and help in closing verification faster.

The design service providers augment the existing teams bringing the required elasticity to the project needs or take up ownership of derivatives and execute them. These engineers are exposed to a variety of flows and methodologies while contributing to different projects. They can help in introducing efficiency to the existing ways of accomplishing tasks. Auditing existing flows and porting the legacy environment to better ones is another way these groups can contribute effectively if partnered aptly.

Finally the software teams that bring life to the HW we verify. In my last blog I highlighted the need for HW & SW teams to work more closely and how verification teams acts as a bridge between the two. Working closely with the SW teams can improve reusability and eliminate redundancies in the efforts.

Collaboration today is the need of the hour! We need to be open to recognize the efforts put in by different stakeholders from the ecosystem to realize a product. Collaboration improves reuse and avoids a lot of wasted efforts in terms of repeated work or incorrect understanding of intent. Above all, the camaraderie developed as part of this process would ensure that any or all these folks are available at any time to jump in the hour of need to cover for unforeseen effects of Murphy’s law.

Drop in your experiences & views with collaboration in the comments section.

HW - SW : Yes, Steve Jobs was right!

The start of the year marked another step forward towards the NEXT BIG THING in semiconductor space with a fleet of companies showcasing interesting products at CES in Las Vegas. In parallel, the VLSI conference 2015 at Bangalore also focused on Internet of Things with industry luminaries sharing their views and many local start-ups busy demonstrating their products. As we march forward to enable everything around us with sensors, integrating connectivity through gateways and associated analytics in the cloud, the need for lower form factors, low power, efficient performance and high security at lowest possible cost in limited time is felt more than ever. While there has been a remarkable progress in SoC development targeting these goals, the end product landing with the users doesn’t always reflect the perceived outcome. What this means is, we are at a point where HW and SW cannot work in silos anymore and they need multiple degrees of collaborations.

To enable this next generation product suites, there is a lot of debate going around the CLOSED & OPEN source development. Every discussion refers to the stories of Apple vs Microsoft/Google or iOS vs Android etc. While an open source definitely accelerates development in different dimensions, we all would agree that some of the major user experiences were delivered in a closed system. Interestingly, this debate is more philosophical! At a fundamental level, the reason for closed development was to ensure the HW and SW teams are tightly bound – a doctrine strongly preached by Steve Jobs. From an engineering standpoint, with limited infrastructure available around that time, a closed approach was an outcome of this thought process. Today, the times have changed and there are multiple options available at different abstraction levels to enable close knitting of HW and SW. 

To start with, the basic architecture exploration phase of partitioning the HW and SW can be enabled with the virtual platforms. With the availability of high level models one can quickly build up a desired system to analyze the bottlenecks and performance parameters. There is work in progress to bring power modelling at this level for early power estimation. A transition to cycle accurate models on this platform further enables early software development in parallel to the SoC design cycle. 

Once the RTL is ready, the emulation platforms accelerate the verification cycle by facilitating the testing to be carried out with the external devices imitating real peripherals. This platform also enables the SW teams to try out the code with the actual RTL that would go onto the silicon. The emulators support performance and power analysis that further aid in ensuring that the target specification for the end product is achieved. 

Next, the advancements in FPGA prototyping space finally gives the required boost to have the entire design run faster ensuring that the complete OS can be booted with use-cases running much ahead of the Si tape-out providing insurance to the end product realization.

This new generation of EDA solutions are enabling the bare metal software development to work in complete conjunction with the hardware thereby exploiting every single aspect of the later. It is the verification team that is morphing itself into a bridge between the HW and SW team enabling the SHIFT LEFT in the product development cycle. While the industry pundits can continue to debate over the closed vs open philosophy, the stage is all set to enable HW SW co-development in a given proximity under either of these cases.

As Steve Jobs believed, the differentiation between a GOOD vs GREAT product is the tight coupling of the underlying HW with the associated SW topped with simplicity of use. Yes, Steve Jobs was right and today we see technology enabling his vision for everyone!

Wish you & your loved ones a Happy and Prosperous 2015!

Disclaimer: The thoughts shared are an individual opinion of the author and not influenced by any corporate.