Shrinking schedules topped with increasing expectations
in terms of more functionality opened up gates for reusability in the
semiconductor industry. Reusability (internal or external) is constantly on a
rise both in design & verification. Following are some of the trends on
reusability presented by Harry Foster at DVCLUB UK, 2013 based on Wilson
Research Group study in 2012, commissioned by Mentor Graphics.
Both IP and SOC now demand periodic releases
targeting specific features for a customer or a particular product category. It is important to be objective in terms of verifying the design for
the given context to ensure the latest verification tools & methodologies do
not dismiss the required focus. With verification claiming most of ASIC design
schedule in terms of efforts & time, conventional schemes fail in managing verification progress and extending predictable closure. There is a need for
a platform that helps in directing the focus of CRV, brings in automation around coverage, provides initial triaging of failures and aids in methodical verification
closure. While a lot of this has been done using in house developed scripts,
there is a significant time spent in maintaining it. There are multiple
solutions available in the market and the beauty of being into consulting is
that you get to play around with most of them considering customer
preferences towards a particular EDA flow.
QVM (Questa Verification Manager)
is one such platform provided by Mentor Graphics. I recently co-authored an
article (QVM : Enabling Organized, Predictable and Faster Verification Closure)
published in Verification Horizons, DAC 2013 edition. This is
available on Verification academy or you can download the paper here too.
