EDA360 Realizations : Verification perspective

EDA360 is all about bringing a CHANGE. A change in perception, planning and execution to bring about a change in the 3Ps that limit our Product. The approach widens the horizons and opens up new avenues for all the stakeholders associated with product development. With involvement of verification team at all levels in the ASIC design cycle, this new theory affects a verification engineer in multiple ways.

-    Movement to a higher abstraction layer demands verification at a new layer. The verification plan now needs to address verification of models at this layer and define an approach to reuse the efforts at following layers. The Verification IP should be portable so as to verify the IP model stand alone and when integrated into an SOC. The verification environment at this level must provide enough hooks to assist in power, performance what-if analysis. It should also have enough APIs to simulate the embedded drivers on this platform.

-   Verification IP needs to become an integral part of IP deliverable. Apart from providing required constraint random infra structure, the VIP should also include a protocol compliance suite to exercise the IP with these vectors at different levels. It must also ensure that the drivers coming as part of the IP stack can be simulated with required modification to the verification environment. Extrapolate this to sub-system or SOC level and we get a list of expectations from the verification environment at different stages of the design integration.

-    With analog claiming more area on the chip, there is a need to define a methodology to verify analog modules. Abstract layers modeling analog blocks needs to be added to ascertain their presence at all levels of design cycle. Verification of these models at different levels, defining a reusable constraint random verification flow, planning a metric driven verification approach, seamless integration verification of analog and digital blocks are major challenges to be taken care for mixed signal designs.

-    Simulating real time scenarios is needed to ensure system level functionality. Hardware acceleration is desired to drive real time data into the design before tape out while reducing simulation turn-around time. Application driven approach requires software to be developed in parallel with the hardware. To test this software early enough Virtual prototyping and emulation are potential solutions. Verification team’s involvement is required at all these levels to reuse the infrastructure and recreating failing scenarios for detailed design debug.

-    Advancement in Verification platforms has been exorbitant. Apart from coverage driven methodology, dashboards (with different views) are available to effectively manage the resources (engineers, hardware and licenses) while tracking the progress. Deploying similar flows to Mixed signal verification, Embedded software verification and System level tracking would help a lot in bringing the teams contributing to the product development together.

EDA360 preaches elimination of redundant verification to reduce cost and improve productivity, profitability and predictability. It proposes sharing the innovation in verification with other areas of the system development. A complete holistic verification is demanded that will eventually lead to more work, more jobs and more $$$ for the verification engineer J   

Related posts -
EDA360 : Realizing what it is?
EDA360 : Realizing the Realizations

EDA 360 : Realizing the Realizations

EDA360 proposes a marriage between hardware and software. Each of them evolved independently and on integration, the final product has been “good enough” but not OPTIMAL. Either the software is unaware of the features in hardware or the hardware is incognizant with the requirements of software. Furthermore, when there is an issue with the system operation, ownership of debugging is a big question mark. EDA360 suggests correction at all levels through 3 realizations.

Silicon Realization – Associated with Creators and Integrators (serving as Creators also), it aims to design (an IP, a sub-system or a chip) for high performance, low power and small form factor. With increasing design complexity, matters related to low power, mixed signal design, 3D IC, DFM and yield are worrying the technocrats more than ever. Within the hardware arena, the tool evolution for functional, physical and electrical domains happened in silos and this constantly hampers efficiency, productivity and predictability. Amidst these technical challenges, pressure of time to market leaves no room for error. To achieve the goal of 3Ps, design teams need to control complexity at a higher abstraction level. This means that all variables of the design process should be accessible i.e. controllable and observable at a higher layer. There is a need for an integrated flow along with unified representation of intent to drive the design from this abstract layer to silicon such that there is interoperability on functional, physical and electrical parameters at each level.

SOC Realization – Associated with Integrators it extends expectations towards Creators. The traditional approach to SOC development is serial i.e. SOC à [OS + SW] à APPS. Each of these steps have least interaction and knowledge sharing, thereby leading to poor Productivity i.e. sub optimal hardware usage and increased failures in the end product. This adds to the cost & delay affecting Predictability and Profitability. Moreover, disjoint teams result into ownership issue (HW or SW problem) if the end product doesn’t behave as expected. SOC realization proposes a potential solution to such problems by treating SOC as a HW that is always accompanied with device drivers. This can be achieved by deploying a top down approach where SOC design and related (embedded) SW development happen in parallel. TLM and virtual prototyping aid in testing these SW layers well in advance before the silicon comes back. Extrapolating this approach sets expectations for IP developers to package the whole stack i.e. TLM, RTL, Netlist, design constraints, VIP and device drivers as part of IP deliverable.

System Realization – It is associated with Integrators. In the conventional flow [HW à SW à APPS], Productivity suffers as, HW is either over designed to support unforeseen applications or under designed limiting application support. This bottom up approach involves minimal planning and no what if analysis leading to poor selection of components (HW, OS, and Drivers etc) for the system. HW SW integration and APPS development happen late and with little knowledge of each other, contributing to inefficiencies and schedule delay [re-verification and ECOs] thereby affecting Profitability. Silicon Realization suggests a top down approach where applications drive the system requirements to overcome such issues and add differentiation as well as competitiveness to the end product. Chip planning tools assist in what if analysis with available set of components for a given architecture to improve predictability. TLM, Virtual prototyping and Emulation tools help with early software development and testing. Latest development in verification when extended at multiple levels provides a defined approach for embedded SW verification and bringing up a controllable & observable dashboard to manage the complete system development lifecycle.

The changing market dynamics has ignited the debate of ‘what should be’ from ‘what is’ available and if it demands a complete change in the way we design our products we better do it now before the next product from competition kicks our product out from the market.      

Related posts -
EDA 360 : Realizing what it is?
EDA360 Realizations : Verification perspective